Automated selection and placement of memory during design of an integrated circuit

• US 20040117744A1
• Filed: 12/13/2002
• Published: 06/17/2004
• Est. Priority Date: 12/13/2002
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Delp, Gary, Nation, George, Reuland, Paul
• Granted Patent: US 7,069,523 B2
• Time in Patent Office: Days
• US Class Current: 716/1
• CPC Class Codes: G06F 2115/06 Structured ASICs
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer'"'"'s requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested. Upon successful testing, the memory manager updates the memory resource database to indicate the successfully tested memory is no longer available as a resource for the generation of further memories. A design integrator may review the memory designs output and further integrate the memory, its timing, testing, etc. with other blocks and functions of the integrated circuit.

Claims

1. A memory generation tool, comprising:

(a) a memory manager having as input a description of a slice and a request for at least one memory;

(b) a memory resource database comprising a plurality of available memory resources of the description;

(c) a memory resource selector capable of selecting candidate memory resources from the available memory resources to satisfy the request;

(d) a memory composer capable of generating at least one memory design from the candidate memory resources to satisfy the request.

2. The memory generation tool of claim 1, wherein the available memory resources comprised diffused memory.

3. The memory generation tool of claim 1, wherein the available memory resources comprises logic gate arrays.

4. The memory generation tool of claim 3, wherein the memory design comprises a synthesis script for a R-cell memory derived from the logic gate array to satisfy the request.

5. The memory generation tool of claim 4, wherein the memory design comprises a second synthesis script for a flop-based memory derived from the logic gate array to satisfy the request.

6. The memory generation tool of claim 1, wherein the memory design comprises a memory wrapper.

7. The memory generation tool of claim 1, wherein the memory manager further maintains the memory resource database.

8. The memory generation tool of claim of claim 7, wherein the memory manager updates the memory resource database to indicate that an available memory resource has been allocated to satisfy the request.

9. The memory generation tool of claim 1, wherein the memory resource selector selects more than one available memory resource to satisfy the request.

10. The memory generation tool of claim 9, wherein the memory resource selector gives priority to the more than one available memory resources that have compatible power and/or timing and/or size.

11. A memory generation tool, comprising:

(a) a memory manager having as input a description of a slice and a request for at least one memory;

(b) a memory resource database comprising a plurality of available memory resources of the description, the available memory resources comprising diffused memory and logic gate arrays, the memory manager to maintain and update the memory resource database to indicate that an available memory resource has been allocated to satisfy the request;

(c) a memory resource selector capable of selecting candidate memory resources from the available memory resources to satisfy the request wherein the memory resource selector gives priority to the available memory resources that have compatible power and/or timing and/or size when selecting candidate memory resources;

(d) a memory composer capable of generating at least one memory design having a plurality of shells, wherein at least one shell is a RTL memory wrapper and others of the plurality of shells comprise synthesis scripts for at least a R-cell memory and a flop-based memory derived from the logic gate array from the candidate memory resources to satisfy the request to indicate that an available memory resource has been allocated to satisfy the request.

12. The memory resource tool of claim 11, further comprising:

(a) a design database of a plurality of hardmacs assigned and configured for a plurality of functions of the integrated circuit;

(b) a design integrator to integrate the at least one memory design into the plurality of functions of the integrated circuit; and

(c) a design qualifier to determine if the at least one memory design is compatible with the plurality of functions of the integrated circuit.

13. An article of manufacture, comprising a data storage medium tangibly embodying a program of machine readable instructions executable by an electronic processing apparatus to perform method steps for operating an electronic processing apparatus, said method steps comprising the steps of:

(a) reading a description of a slice having at least one memory of either diffused and/or gate array logic;

(b) reading a specification of at least one requested memory for an integrated circuit;

(c) determining if the specification of the at least one requested memory can be generated from the description of the slice;

(d) allocating a portion of the at least one memory of either diffused and/or gate array logic of the description of the slice to the at least one requested memory;

(e) generating a logic infrastructure for the allocated portion;

(f) creating a memory design of the allocated portion; and

(g) updating a memory resource database to indicate the allocated portion is not available for anymore of the at least one requested memories

14. The article of manufacture of claim 13, wherein the method steps embodied in the program of machine readable instructions executable by an electronic processing apparatus further comprises the steps of:

(a) determining if the specification of another of the at least one requested memory can be generated from the description of the slice;

(b) allocating another portion of the at least one memory of either diffused and/or gate array logic of the description of the slice to the another memory;

(c) generating a logic infrastructure for the another allocated portion;

(f) creating a memory design of the another allocated portion; and

(g) updating a memory resource database to indicate the another allocated portion is not available for anymore of the at least one requested memories

15. A method of generating memory designs for an integrated circuit, comprising the steps of:

(a) inputting available memory resources into a memory resource database;

(b) inputting a request for at least one memory;

(c) selecting possible memory resources from the available memory resources to satisfy the request.

16. The method of claim 15, wherein the step of selecting further comprises considering the size, power, timing characteristics of the possible memory resources to satisfy the request.

17. The method of claim 16, further comprising generating a memory design to satisfy the request from one or more of the following possible memory resources:

diffused memory, R-cell memory, flop-based memory.

18. The method of claim 17, further comprising generating a memory design by combining two or more possible memory resources having compatible size, power, and timing characteristics to satisfy the request.

19. A memory generation tool further comprising:

(a) means to read a slice description having at least one diffused and/or gate array logic;

(b) means to read a specification of requested memory;

(c) means to determine if the requested memory can be generated from the at least one diffused and/or gate array logic;

(d) if not, means to notify a user;

(e) if so, means to allocate a portion of the at least one diffused and/or gate array logic to the requested memory;

(f) means to determine if there is additional diffused and/or gate array logic available;

(g) means to determine if there is a second requested memory;

(h) means to allocate a second portion of the additional diffused and/or gate array logic to the second requested memory;

(i) means to combine one or more portions of the diffused and/or gate array logic together to allocate to the requested memory;

(j) means to generate a memory wrapper for the allocated portions; and

(k) means to generate memory designs of the allocated portions and the memory wrapper.