Electrostatic imager

• US 20040118991A1
• Filed: 12/18/2002
• Published: 06/24/2004
• Est. Priority Date: 12/18/2002
• Status: Active Grant

• Current Assignee: Varex Imaging Corporation
• Original Assignee: Varian Medical Systems Incorporated (Siemens AG)
• Inventors: Zentai, George, Colbeth, Richard, Yamaoka, Shuji
• Granted Patent: US 6,921,892 B2
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: G03G 5/00 Recording members for original recording by exposure, e.g. to light, to heat, to electrons; Manufacture thereof; Selection of materials therefor recording surfaces for measuring apparatus G01D15/34; photosensitive materials for photographic purposes G03C
• CPC Class Codes: G03G 5/0202 Dielectric layers for electrography
• CPC Class Codes: H01L 27/14679 Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers

Abstract

An apparatus and method for detecting an electrostatic charge on a flat panel imager pixel array. In one embodiment, the apparatus includes an insulator layer and a flat panel pixel array coupled to a bottom surface of the insulator layer. Each pixel of the pixel array has a storage capacitance, and an electrostatic charge corresponding to a voltage applied through an electrode coupled to a top surface of the insulating layer may be detected from each storage capacitance.

Claims

1. An apparatus, comprising:

an insulator layer having a bottom surface and a top surface; and

a flat panel imaging pixel array coupled to the bottom surface of the insulator layer, wherein each pixel of the pixel array has a storage capacitance, and wherein an electrostatic charge corresponding to a voltage applied through an electrode coupled to the top surface of the insulating layer may be detected from each storage capacitance.

2. The apparatus of claim 1, wherein the flat panel imaging pixel array comprises an amorphous silicon (“

a-Si”

) pixel array.

3. The apparatus of claim 2, wherein the a-Si pixel array is the basis for a thin film transistor (“

TFT”

) flat panel detector.

4. The apparatus of claim 2, wherein the a-Si pixel array is the basis for a single switching diode flat panel detector.

5. The apparatus of claim 2, wherein the a-Si pixel array is the basis for a double switching diode flat panel detector.

6. The apparatus of claim 2, further comprising a readout transistor coupled to each storage capacitance, wherein the readout transistor transmits a signal corresponding to the electrostatic charge.

7. The apparatus of claim 6, further comprising a processor to receive the signal from each readout transistor corresponding to the electrostatic charge.

8. The apparatus of claim 7, further comprising a power source coupled to the flat panel imaging pixel array and the processor.

9. The apparatus of claim 8, further comprising a substrate layer disposed below and coupled to the flat panel imaging pixel array.

10. The apparatus of claim 9, further comprising an analog to digital converting (“

ADC”

) board disposed below and coupled to the substrate layer.

11. The apparatus of claim 1, wherein the flat panel imaging pixel array comprises a polycrystalline silicon (“

p-Si”

) pixel array.

12. The apparatus of claim 1, wherein the flat panel imaging pixel array comprises an organic semiconductor pixel array.

13. The apparatus of claim 9, wherein the substrate layer comprises an insulating material.

14. The apparatus of claim 13, wherein the substrate layer comprises glass.

15. The apparatus of claim 13, wherein the substrate layer comprises a ceramic material.

16. An apparatus, comprising:

an insulator layer having a top surface and a bottom surface; and

an electrostatic detector having a flat panel imaging pixel array coupled to the bottom surface of the insulator layer, wherein each pixel of the pixel array has a storage capacitance, and wherein an electrostatic charge corresponding to a voltage applied through a conductive trace from a circuit board coupled to the top surface of the insulating layer may be detected from each storage capacitance.

17. The apparatus of claim 16, wherein the flat panel imaging pixel array comprises an a-Si pixel array.

18. The apparatus of claim 17, wherein the a-Si pixel array is the basis for a TFT flat panel detector.

19. The apparatus of claim 17, wherein the a-Si pixel array is the basis for a single switching diode flat panel detector.

20. The apparatus of claim 17, wherein the a-Si pixel array is the basis for a double switching diode flat panel detector.

21. The apparatus of claim 17, further comprising a readout transistor coupled to each storage capacitance, wherein the readout transistor transmits a signal corresponding to the electrostatic charge.

22. The apparatus of claim 21, further comprising a processor to receive the signal from each readout transistor corresponding to the electrostatic charge.

23. The apparatus of claim 22, further comprising a power source coupled to the electrostatic detector and the processor.

24. The apparatus of claim 23, further comprising a substrate layer disposed below and coupled to the flat panel imaging pixel array.

25. The apparatus of claim 24, further comprising an analog to digital converting (“

ADC”

) board disposed below and coupled to the substrate layer.

26. The apparatus of claim 16, wherein the flat panel imaging pixel array comprises a polycrystalline silicon (“

p-Si”

) pixel array.

27. The apparatus of claim 16, wherein the flat panel imaging pixel array comprises an organic semiconductor pixel array.

28. The apparatus of claim 24, wherein the substrate layer comprises an insulating material.

29. The apparatus of claim 28, wherein the substrate layer comprises glass.

30. The apparatus of claim 28, wherein the substrate layer comprises a ceramic material.

31. A system, comprising:

an electrostatic receptor having a flat panel imaging pixel array that detects a capacitive charge and transmits a signal corresponding to the capacitive charge;

a power supply coupled to the electrostatic receptor; and

a processor coupled to the receptor;

wherein the processor generates an image data based on the signal received from the electrostatic receptor.

32. The system of claim 31, wherein the capacitive charge is generated from an electric pulse applied to a conductive trace coupled to the electrostatic receptor.

33. The system of claim 31, wherein the flat panel imaging pixel array comprises an a-Si pixel array.

34. The system of claim 33, wherein the electrostatic receptor further comprises:

a top insulator layer;

a TFT pixel array disposed below and coupled to the top insulator layer;

a substrate layer disposed below and coupled to the TFT pixel array.

35. The system of claim 34, further comprising a workstation coupled to the processor, wherein the workstation receives the image data from the processor.

36. A method, comprising:

capacitively coupling a conductive trace to an electrostatic detector having a flat panel imaging pixel array; and

producing an image of the conductive trace based on a measured capacitive charge at each pixel from the flat panel pixel array.

37. The method of claim 36, further comprising applying a voltage to the conductive trace.

38. The method of claim 37, further comprising measuring the capacitive charge based on the applied voltage.

39. The method of claim 36, further comprising identifying defective pixels on the electrostatic detector.

40. The method of claim 39, further comprising generating a map file of the defective pixels.

41. The method of claim 36, further comprising calibrating a gain value for the signal.

42. The method of claim 36, further comprising calibrating an offset value for the signal.

43. The method of claim 39, further comprising replacing the signal from a defective pixel with a corrected signal.

44. The method of claim 41, wherein calibrating the gain value comprises:

detecting a plurality of test images uniformly stimulated over the entire electrostatic detector; and

summing an absolute value of positive and negative images.

45. The method of claim 42, wherein calibrating the offset value comprises:

applying a plurality of blank images files to the electrostatic detector; and

averaging a signal from the plurality of blank image files at each pixel.

46. An apparatus, comprising:

means for capacitively coupling a conductive trace to an electrostatic detector having a flat panel imaging pixel array; and

means for producing an image of the conductive trace based on a measured capacitive charge at each pixel from the flat panel pixel array.

47. The apparatus of claim 46, further comprising means for applying a voltage to the conductive trace.

48. The apparatus of claim 47, further comprising means for measuring the capacitive charge based on the applied voltage.

49. The apparatus of claim 46, further comprising means for identifying defective pixels on the electrostatic detector.

50. The apparatus of claim 49, further comprising means for generating a map file of the defective pixels.

51. The apparatus of claim 46, further comprising means for calibrating a gain value for the signal.

52. The apparatus of claim 46, further comprising means for calibrating an offset value for the signal.

53. The apparatus of claim 49, further comprising means for replacing the signal from a defective pixel with a corrected signal.

54. The apparatus of claim 51, wherein means for calibrating the gain value comprises:

means for detecting a plurality of test images uniformly stimulated over the entire electrostatic detector; and

means for summing an absolute value of positive and negative images.

55. The apparatus of claim 52, wherein means for calibrating the offset value comprises:

means for applying a plurality of blank images files to the electrostatic detector; and

means for averaging a signal from the plurality of blank image files at each pixel.

56. A machine-readable medium having stored thereon instructions, which when executed by a processor, causes the processor to perform the following:

measuring a capacitive charge on an electrostatic detector, having flat panel imaging pixel array, based on an applied voltage;

generating a signal based on the capacitive charge measured at a pixel from a pixel array; and

producing an image of the conductive trace based on the signal.

57. The machine readable medium of claim 56, wherein the processor further performs identifying defective pixels on the electrostatic detector.

58. The machine readable medium of claim 57, wherein the processor further performs generating a map file of the defective pixels.

59. The machine readable medium of claim 58, wherein the processor further performs calibrating a gain value for the signal.

60. The machine readable medium of claim 59, wherein the processor further performs calibrating an offset value for the signal.

61. The machine readable medium of claim 60, wherein the processor further performs replacing the signal from a defective pixel with a corrected signal.