Non-volatile memory cells having floating gate and method of forming the same
First Claim
1. A non-volatile memory cell comprising:
- a device isolation layer disposed in a substrate to define an active region;
a floating gate disposed over the active region and comprised of a plurality of first conductive patterns and a plurality of second conductive patterns which are alternately stacked; and
a first insulation layer interposed between the floating gate and the active region, wherein one of the first and second conductive patterns protrudes to form concave and convex shaped sidewalls of the floating gate.
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Abstract
A non-volatile memory cell having a floating gate and a method of forming the same. The non-volatile memory cell includes a device isolation layer that is formed in a semiconductor substrate and defines an active region. A floating gate is disposed over the active region and is comprised of a plurality of first conductive patterns and a plurality of second conductive patterns that are alternately stacked. A first insulation layer is disposed between the floating gate and the active region. One of the first conductive pattern and the second conductive pattern protrudes to form concave and convex sidewalls of the floating gate. Therefore, a surface area of the floating gate increases, thereby raising coupling ratio between the floating gate and the control gate electrode. As a result, an operating voltage of the non-volatile memory cell can be reduced.
39 Citations
28 Claims
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1. A non-volatile memory cell comprising:
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a device isolation layer disposed in a substrate to define an active region;
a floating gate disposed over the active region and comprised of a plurality of first conductive patterns and a plurality of second conductive patterns which are alternately stacked; and
a first insulation layer interposed between the floating gate and the active region, wherein one of the first and second conductive patterns protrudes to form concave and convex shaped sidewalls of the floating gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a non-volatile memory cell comprising:
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forming a device isolation layer in a semiconductor substrate to define an active region;
forming a first insulation layer over the active region;
forming a gate conductive layer over an entire surface of the semiconductor substrate with the first insulation layer, wherein the gate conductive layer comprises a plurality of first conductive layers and second conductive layers that are alternately stacked; and
forming a floating gate with concave and convex sidewalls by applying a patterning process including an isotropic etching of the gate conductive layer, wherein the isotropic etching has etch selectivity with respect to the first and second conductive layers. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A non-volatile memory cell comprising:
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a substrate;
an active region formed in the substrate; and
a floating gate having sidewalls formed over the active region, the sidewalls having protruding portions. - View Dependent Claims (21, 22, 23, 24)
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25. A method of forming a non-volatile memory cell comprising:
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forming an active region in a semiconductor substrate; and
forming a floating gate having sidewalls over the active region, the sidewalls having protruding portions. - View Dependent Claims (26, 27, 28)
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Specification