Buried-gate-type semiconductor device

• US 20040119117A1
• Filed: 12/11/2003
• Published: 06/24/2004
• Est. Priority Date: 12/24/2002
• Status: Active Grant

• Current Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: Toyoda Jidosha Kabushiki Kaisha
• Inventors: Kushida, Tomoyoshi
• Granted Patent: US 7,038,275 B2
• Time in Patent Office: Days
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7392 with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

An object of this invention is to provide a buried gate-type semiconductor device in which its gate interval is minimized so as to improve channel concentration thereby realizing low ON-resistance, voltage-resistance depression due to convergence of electrical fields in the vicinity of the bottom of the gate is prevented and further prevention of voltage-resistance depression and OFF characteristic are achieved at the same time. A plurality of gate electrodes 106 each having a rectangular section are disposed in its plan section. The interval 106T between the long sides of the gate electrodes 106 is made shorter than the interval 106S between the short sides thereof. Further, a belt-like contact opening 108 is provided between the short sides of the gate electrode 106, so that P⁺ source region 100 and N⁺ source region 104 are in contact with a source electrode. Consequently, the interval 106T between the long sides of the gate electrode 106 can be set up regardless of the width of the contact opening 108.

Claims

1. A buried-gate-type semiconductor device comprising:

a semiconductor substrate;

a first one-conduction-type semiconductor region formed in the semiconductor substrate;

a first other-conduction-type semiconductor region formed above of the first one-conduction-type semiconductor region;

a plurality of buried gates buried in the semiconductor substrate penetrating the first other-conduction-type semiconductor region, the buried gates having long sides and short sides intersecting to one another in a section parallel to a surface of the semiconductor substrate, and being arranged repeatedly along at least short-side direction;

a second one-conduction-type semiconductor region formed at a surface side of the first other-conduction-type semiconductor region;

a second other-conduction-type semiconductor region having a bottom portion deeper than a bottom portion of buried gates, the second other-conduction-type semiconductor region being at least formed at a side portion of a buried gate'"'"'s short side; and

a wiring layer,

wherein a contact portion at which the second one-conduction-type semiconductor region and the wiring layer are in contact with each other is arranged at a buried gate'"'"'s short side.

2. A buried-gate-type semiconductor device according to claim 1, wherein the second other-conduction-type semiconductor region covers a shoulder portion that is a cross portion of a side surface at a side of a buried gate'"'"'s short side and a bottom surface of the buried gate.

3. A buried-gate-type semiconductor device according to claim 1, wherein buried gates are arranged repeatedly along a long-side direction as well, and an interval between a buried gate'"'"'s long side and another buried gate'"'"'s long side is shorter than an interval between a buried gate'"'"'s short side and another buried gate'"'"'s short side.

4. A buried-gate-type semiconductor device according to claim 1 further comprising a bottom-surface other-conduction-type semiconductor region at a bottom face of the first one-conduction-type semiconductor region, opposite to the first other-conduction-type semiconductor region.

5. A buried-gate-type semiconductor device comprising:

a semiconductor substrate;

a first one-conduction-type semiconductor region formed in the semiconductor substrate;

a channel semiconductor region of other-conduction-type formed above of the first one-conduction-type semiconductor region;

a plurality of buried gates buried in the semiconductor substrate penetrating the channel semiconductor region, the buried gates having long sides and short sides intersecting to one another in a section parallel to a surface of the semiconductor substrate, and being arranged repeatedly at least along short-side direction;

a second one-conduction-type semiconductor region formed at a surface side of the channel semiconductor region;

an embedded other-conduction-type semiconductor region having a bottom portion deeper than a bottom portion of buried gates, the embedded other-conduction-type semiconductor region being at least formed at a side portion of a buried gate'"'"'s short side; and

a wiring layer,

wherein a contact portion at which the second one-conduction-type semiconductor region and the wiring layer are in contact with each other is arranged at a buried gate'"'"'s short side.

6. A buried-gate-type semiconductor device according to claim 5, wherein the embedded other-conduction-type semiconductor region covers a shoulder portion that is a cross portion of a side surface at a side of a buried gate'"'"'s short side and a bottom surface of the buried gate.

7. A buried-gate-type semiconductor device according to claim 5, wherein buried gates are arranged repeatedly along a long-side direction as well, and an interval between a buried gate'"'"'s long side and another buried gate'"'"'s long side is shorter than an interval between a buried gate'"'"'s short side and another buried gate'"'"'s short side.

8. A buried-gate-type semiconductor device according to claim further comprising a bottom-surface other-conduction-type semiconductor region at a bottom face of the first one-conduction-type semiconductor region, opposite to the channel semiconductor region.

9. A buried-gate-type semiconductor device comprising:

a semiconductor substrate;

a first one-conduction-type semiconductor region formed in the semiconductor substrate;

a channel semiconductor region formed above of the first one-conduction-type semiconductor region;

a plurality of buried gates buried in the semiconductor substrate penetrating the channel semiconductor region, the buried gates having long sides and short sides intersecting to one another in a section parallel to a surface of the semiconductor substrate, and being arranged repeatedly at least along short-side direction;

a second one-conduction-type semiconductor region formed at a surface side of the channel semiconductor region;

a gate-side-portion other-conduction-type semiconductor region having a bottom portion deeper than a bottom portion of buried gates, the gate-side-portion other-conduction-type semiconductor region being at least formed at a side portion of a buried gate'"'"'s short side; and

a wiring layer,

wherein a contact portion at which the second one-conduction-type semiconductor region and the wiring layer are in contact with each other is arranged at a buried gate'"'"'s short side,

impurity concentration at between buried gates in the channel semiconductor region is lower than impurity concentration at the first one-conduction-type semiconductor region, and

entirety of the channel semiconductor region gets depleted in case applied voltage to buried gates is 0 or opposite bias.

10. A buried-gate-type semiconductor device according to claim 9, wherein the gate-side-portion other-conduction-type semiconductor region covers a shoulder portion that is a cross portion of a side surface at a side of a buried gate'"'"'s short side and a bottom surface of the buried gate.

11. A buried-gate-type semiconductor device according to claim 9, wherein buried gates are arranged repeatedly along a long-side direction as well, and an interval between a buried gate'"'"'s long side and another buried gate'"'"'s long side is shorter than an interval between a buried gate'"'"'s short side and another buried gate'"'"'s short side.

12. A buried-gate-type semiconductor device according to claim 9 further comprising a bottom-surface other-conduction-type semiconductor region at a bottom face of the first one-conduction-type semiconductor region, opposite to the channel semiconductor region.

13. A buried-gate-type semiconductor device comprising:

a semiconductor substrate;

a first one-conduction-type semiconductor region formed in the semiconductor substrate;

a channel semiconductor region formed above of the first one-conduction-type semiconductor region;

a plurality of buried gates buried in the semiconductor substrate penetrating the channel semiconductor region, the buried gates having long sides and short sides intersecting to one another in a section parallel to a surface of the semiconductor substrate, and being arranged repeatedly at least along short-side direction;

a second one-conduction-type semiconductor region formed at a surface side of the channel semiconductor region;

an embedded other-conduction-type semiconductor region having a bottom portion deeper than a bottom portion of buried gates, the embedded other-conduction-type semiconductor region being at least formed at a side portion of a buried gate'"'"'s short side; and

a wiring layer,

wherein a contact portion at which the second one-conduction-type semiconductor region and the wiring layer are in contact with each other is arranged at a buried gate'"'"'s short side,

impurity concentration at between buried gates in the channel semiconductor region is lower than impurity concentration at the first one-conduction-type semiconductor region, and

entirety of the channel semiconductor region gets depleted in case applied voltage to buried gates is 0 or opposite bias.

14. A buried-gate-type semiconductor device according to claim 13, wherein the embedded other-conduction-type semiconductor region covers a shoulder portion that is a cross portion of a side surface at a side of a buried gate'"'"'s short side and a bottom surface of the buried gate.

15. A buried-gate-type semiconductor device according to claim 13, wherein buried gates are arranged repeatedly along a long-side direction as well, and an interval between a buried gate'"'"'s long side and another buried gate'"'"'s long side is shorter than an interval between a buried gate'"'"'s short side and another buried gate'"'"'s short side.

16. A buried-gate-type semiconductor device according to claim 13 further comprising a bottom-surface other-conduction-type semiconductor region at a bottom face of the first one-conduction-type semiconductor region, opposite to the channel semiconductor region.

17. A buried-gate-type semiconductor device comprising:

a semiconductor substrate;

a first one-conduction-type semiconductor region formed in the semiconductor substrate;

a channel semiconductor region formed above of the first one-conduction-type semiconductor region;

a buried gate facing to the channel semiconductor region, the buried gate being formed to reach the first one-conduction-type semiconductor region; and

an other-conduction-type semiconductor region formed in the semiconductor substrate, the other-conduction-type semiconductor region having a bottom portion deeper than a bottom portion of the buried gate and facing to the buried gate.

18. A buried-gate-type semiconductor device according to claim 17, wherein impurity concentration in the channel semiconductor region is lower than impurity concentration at the first one-conduction-type semiconductor region, and entirety of the channel semiconductor region gets depleted in case applied voltage to the buried gate is 0 or opposite bias.

19. A buried-gate-type semiconductor device according to claim 17 further comprising a bottom-surface other-conduction-type semiconductor region at a bottom face of the first one-conduction-type semiconductor region, opposite to the channel semiconductor region.

20. A buried-gate-type semiconductor device according to claim 18 further comprising a bottom-surface other-conduction-type semiconductor region at a bottom face of the first one-conduction-type semiconductor region, opposite to the channel semiconductor region.