Testable electrostatic discharge protection circuits

• US 20040119118A1
• Filed: 04/24/2003
• Published: 06/24/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Chan, Wai Tien, Cornell, Michael E.
• Granted Patent: US 6,906,386 B2
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05138 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/62 : Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 27/0266 : using field effect transistors as protective elements
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7808 : the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/12035 : Zener diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10S 257/904 : with passive components,, e.g. polysilicon resistors

Abstract

A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.

Claims

1. A method for manufacturing a semiconductor device, comprising:

fabricating a die comprising a device having a first bonding pad and ESD protection circuitry having a second bonding pad;

testing the device using a test system electrically connected to the first bonding pad; and

after testing, connecting the first bonding pad to the second bonding pad, wherein the ESD protection circuitry becomes functional to protect the device against electrostatic discharge after connecting the first bonding pad to the second bonding pad.

2. The method of claim 1, wherein the device comprises a power MOSFET, and the die comprises a gate pad that is connected to a gate of the power MOSFET in the die.

3. The method of claim 2, wherein testing the device comprises applying to the gate of the power MOSFET a voltage that is higher than the ESD protection circuitry permits when the ESD protection circuitry is functional.

4. The method of claim 2, wherein the first bonding pad is the gate pad of the power MOSFET.

5. The method of claim 2, wherein the first bonding pad is a source pad that is connected to a source of the power MOSFET.

6. The method of claim 1, wherein before connecting the first bonding pad to the second bonding pad, the method further comprises testing the ESD protection circuitry using a test system that is electrically connected to the second bonding pad.

7. The method of claim 1, wherein testing is performed while the die is part of a wafer containing multiple dice.

8. The method of claim 7, wherein connecting the first bonding pad to the second bonding pad is performed after the die is separated from the wafer.

9. The method of claim 1, wherein connecting the first bonding pad to the second bonding pad is performed during packaging of the die.

10. The method of claim 1, wherein connecting the first bonding pad to the second bonding pad comprises forming a wire bond that contacts the first bonding pad and the second bonding pad.

11. The method of claim 1, wherein connecting the first bonding pad to the second bonding pad comprises:

connecting a first wire to the first bonding pad and to a portion of a lead frame; and

connecting a second wire to the second bonding pad and to the portion of the lead frame.

12. The method of claim 11, wherein the portion of the lead frame includes an external lead that provides an electrical connection to the first and second bonding pads in a package containing the die.

13. The method of claim 1, wherein connecting the first bonding pad to the second bonding pad comprises:

forming a first conductive bump on the first bonding pad;

forming a second conductive bump on the second bonding pad; and

connecting the first conductive bump and the second conductive bump to a conductive region.

14. The method of claim 13, wherein connecting the first and second conductive bumps to a conductive region comprises:

bringing a face of the die on which the first and second conductive bumps were formed into contact with a substrate including the conductive region; and

performing a reflow process that attaches the conductive bumps to the conductive region.

16. A method for manufacturing a semiconductor device, comprising:

fabricating a die comprising a device having a first bonding pad and ESD protection circuitry having a second bonding pad;

testing the ESD protection circuitry using a test system electrically connected to the second bonding pad; and

after testing, connecting the first bonding pad to the second bonding pad, wherein the ESD protection circuitry becomes functional to protect the device against electrostatic discharge after connecting the first bonding pad to the second bonding pad.

17. A semiconductor device including a die that comprises:

a transistor having a first bonding pad; and

ESD protection circuitry having a second bonding pad, wherein the ESD protection circuitry becomes functional to protect the device against electrostatic discharge only after connecting the first bonding pad to the second bonding pad.

18. The device of claim 17, wherein the ESD protection circuitry comprises:

a first diode having an anode connected to the second bonding pad; and

a second diode having a cathode connected to a cathode of the first diode.

19. The device of claim 18, wherein the anode of the second diode is electrically connected to a gate of the transistor.

20. The device of claim 19, further comprising a resistive element that electrically connects the anode of the second diode to the gate of the transistor.

21. The device of claim 19, wherein within the die, the first bonding pad electrically connects to a source of the transistor.

22. The device of claim 18, wherein the anode of the second diode is electrically connected to a source of the transistor.

23. The device of claim 22, wherein within the die, the first bonding pad electrically connects to a gate of the transistor.

24. The device of claim 17, wherein the die further comprises an insulating layer overlying the transistor and the ESD protection circuitry, the insulating layer including a contiguous opening that exposes a portion of the first bonding pad and a portion of the second bonding pad.

25. The device of claim 24, further comprising a wire bond in the opening in the insulating layer, wherein the wire bond extends across a gap between the first and second bonding pads and electrically connects the first bonding pad to the second bonding pad.

26. The device of claim 25, further comprising:

a lead frame; and

a wire extending from the wire bond to a portion of the lead frame.

27. The device of claim 17, further comprising:

a lead frame;

a first wire bonded to the first bonding pad and the lead frame; and

a second wire bonded to the second bonding pad and the lead frame, wherein the first and second bonding pads are electrically connected via the first and second wires and the lead frame.

28. The device of claim 17, further comprising:

a first conductive bump on the first bonding pad;

a second conductive bump on the second bonding pad; and

a conductive region attached to the first and second conductive bumps.

29. The device of claim 28, wherein the conductive region is part of a substrate that is bonded to the die for formation of a flip-chip package.