Multiple dice package

• US 20040119150A1
• Filed: 12/19/2002
• Published: 06/24/2004
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Drye, James E., Hwang, Lih-Tyng, Kuo, Shun Meen
• Granted Patent: US 6,906,406 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/854 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor device for multiple dice is provided that reduces insertion loss and return loss. In an example embodiment, the semiconductor device comprises: a package 20 comprising a mount surface 14 to which dice 61 and 65 are mounted, and a bond pad surface 25 defining at least a first die area 27 and a second die area 29, wherein the second die area 29 is different in form from the first die area 27.

Claims

1. A semiconductor device for multiple die, the device comprising:

a package comprising;

a bond pad surface defining a cavity having at least a first die area and a second die area,

wherein the second die area is different in form from the first die area;

a first semiconductor die mounted in the first die area; and

a second semiconductor die mounted in the second die area.

2. A semiconductor device as in claim 1 further comprising a ground layer under the bond pad surface.

3. A semiconductor device as in claim 2 wherein the ground layer is between the mount surface and the bond pad surface.

4. A semiconductor device as in claim 2 further comprising signal bond pads and ground bond pads on the bond pad surface, wherein at least one signal bond pad and at least one ground bond pad are of different sizes.

5. A semiconductor device as in claim 4 wherein the ground layer is between the mount surface and the bond pad surface.

6. A semiconductor device as in claim 1 further comprising a first set of package bond pads on the bond pad surface wherein at least two of the first set of package bond pads have impedances that are different from each other.

7. A semiconductor device as in claim 1 further comprising a second set of package bond pads on the bond pad surface wherein at least two of the second set of package bond pads have impedances that are different from each other.

8. A semiconductor device as in claim 1 further comprising:

a first set of package bond pads on the bond pad surface having a substantially uniform impedance and

a second set of package bond pads on the bond pad surface having substantially different impedances.

9. A semiconductor device as in claim 8 wherein at least one package bond pad of the first set of package bond pads has an impedance that is different from at least one package bond pad of the second set of package bond pads.

10. A semiconductor device as in claim 8 wherein at least one package bond pad of the second set of package bond pads has an impedance substantially different from another package bond pad of the second set of package bond pads.

11. A semiconductor device as in claim 8 wherein at least two of the second set of package bond pads have substantially different shapes.

12. A semiconductor device as in claim 8 wherein at least two of the second set of package bond pads comprise materials having substantially different impedances.

13. A semiconductor device as in claim 1 wherein a wire bond between at least one package bond pad of the second die area and a die bond pad of the second semiconductor die is less than about 2 millimeters.

14. A semiconductor device as in claim 13 wherein the wire bond is less than about 1 millimeter.

15. A semiconductor device as in claim 1 wherein an edge of the cavity in the second die mount area is between about 20 microns and about 50 microns from a bond surface edge.

16. A semiconductor device as in claim 1 wherein the second die area closely conforms to the second semiconductor die.

17. A semiconductor device as in claim 1 wherein the first semiconductor die comprises a control die and the second semiconductor device comprises a RF device.

18. A semiconductor device as in claim 17 further wherein the RF device comprises a MEMS device.

19. A package for multiple semiconductor dice, the package comprising:

a die mount surface;

a bond pad surface residing over the die mount surface,

wherein the bond pad surface includes a cavity having

a first portion defining a first generally rectangular die receiving area and

a second portion defining a second generally rectangular die receiving area, and

wherein the first and the second die receiving areas have differing dimensions;

a first set of package bond pads on the bond pad surface proximate to the first portion of the cavity; and

a second set of package bond pads on the bond pad surface proximate to the second portion of the cavity.

20. A package as in claim 19 wherein at least one of the first set of package bond pads on the bond pad surface has an impedance different from the impedance of at least one of the second set of package bond pads on the bond pad surface.

21. A package as in claim 19 wherein at least one of the first set of package bond pads on the bond pad surface has an impedance different from the impedance of another of the first set of package bond pads on the bond pad surface.

22. A package as in claim 19 wherein at least one of the second set of package bond pads on the bond pad surface has an impedance different from the impedance of another of the second set of package bond pads on the bond pad surface.

23. A package as in claim 19 further comprising a first semiconductor die mounted to the die mount surface in the first generally rectangular die receiving area and a second semiconductor die mounted to the die mount surface in the second generally rectangular die receiving area.

24. A package as in claim 23 wherein the second semiconductor die is less than about 50 microns from the bond surface.

25. A package as in claim 24 wherein the second semiconductor die is more than about 20 microns from the bond surface.

26. A package as in claim 23 further comprising a wire bond between a die bond pad on the second semiconductor die and a package bond pad, wherein the wire bond is less than about 2 millimeters in length.

27. A package as in claim 26 wherein the wire bond is less than about 1 millimeter in length.

28. A package as in claim 23 wherein the first semiconductor die comprises a control device and the second semiconductor die comprises a RF device.

29. A package as in claim 28 wherein the RF device comprises a MEMS device.

30. A package as in claim 23 further comprising a third semiconductor die connected in the first generally rectangular die receiving area to the first semiconductor die.

31. A package as in claim 30 wherein the third semiconductor die is mounted to the first semiconductor die.

32. A package as in claim 30 wherein the third semiconductor die is mounted to the die mount surface.

33. A package as in claim 23 further comprising a third semiconductor die connected in the second generally rectangular die receiving area to the second semiconductor die.

34. A package as in claim 33 wherein the second semiconductor die comprises an IPD and the third semiconductor die comprises a MEMS device mounted to the IPD.