Multichip package test
First Claim
Patent Images
1. A test apparatus, comprising:
- a test driver including a drive channel and an input/output channel; and
a test board including a package, the package having mounted thereon a plurality of chips;
where the drive channel connects to drive pins associated with each of the plurality of chips in parallel; and
where the input/output channel connects to input/output pins associated with each of the plurality of chips in parallel.
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Abstract
A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.
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Citations
6 Claims
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1. A test apparatus, comprising:
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a test driver including a drive channel and an input/output channel; and
a test board including a package, the package having mounted thereon a plurality of chips;
where the drive channel connects to drive pins associated with each of the plurality of chips in parallel; and
where the input/output channel connects to input/output pins associated with each of the plurality of chips in parallel. - View Dependent Claims (2, 3, 4)
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5. A method of testing a package mounted with a plurality of semiconductor chips, comprising:
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connecting a drive channel of a test driver to a plurality of drive pins corresponding to the plurality of semiconductor chips;
connecting an input/output channel of a test driver to a plurality of input/output pins corresponding to the plurality of semiconductor chips; and
setting, while one of the semiconductor chips is being tested, the drive and input/output pins of other semiconductor chips to a high impedance state. - View Dependent Claims (6)
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Specification