Multichip package test

• US 20040119491A1
• Filed: 10/01/2003
• Published: 06/24/2004
• Est. Priority Date: 10/01/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Ju, Ki-Bong, Kwon, Hyuk, Shim, Hyun-Seop, Lee, Hyoung-Young, Shin, Young-Gu, Heo, Kyoung-Il, Bang, Jeong-Ho
• Granted Patent: US 6,943,577 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls

Abstract

A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Claims

1. A test apparatus, comprising:

a test driver including a drive channel and an input/output channel; and

a test board including a package, the package having mounted thereon a plurality of chips;

where the drive channel connects to drive pins associated with each of the plurality of chips in parallel; and

where the input/output channel connects to input/output pins associated with each of the plurality of chips in parallel.

2. The test apparatus of claim 1 where while one of the semiconductor chips is being tested the drive and input/output pins of other semiconductor chips are held in a high impedance state.

3. The test apparatus of claim 2 where the semiconductor chips are tested sequentially.

4. The test apparatus of claim 1 where the drive pins includes control and address pins.

5. A method of testing a package mounted with a plurality of semiconductor chips, comprising:

connecting a drive channel of a test driver to a plurality of drive pins corresponding to the plurality of semiconductor chips;

connecting an input/output channel of a test driver to a plurality of input/output pins corresponding to the plurality of semiconductor chips; and

setting, while one of the semiconductor chips is being tested, the drive and input/output pins of other semiconductor chips to a high impedance state.

6. The method of claim 5 where the drive pins include control and address pins.