AC powered logic circuitry

• US 20040119504A1
• Filed: 12/23/2002
• Published: 06/24/2004
• Est. Priority Date: 12/23/2002
• Status: Active Grant

• Current Assignee: 3M Innovative Properties Company (3M Company)
• Original Assignee: 3M Innovative Properties Company (3M Company)
• Inventors: Haase, Michael A., Baude, Paul F.
• Granted Patent: US 7,088,145 B2
• Time in Patent Office: Days
• US Class Current: 326/104
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

The use of an alternating current (ac) source to power logic circuitry can support satisfactory device performance for a variety of applications, while enhancing long-term stability of the circuitry. For example, when organic thin film transistor (OTFT)-based logic circuitry is powered by an ac power source, the logic circuitry exhibits stable performance characteristics over an extended period of operation. Enhanced stability may permit the use of OTFT logic circuitry to form a variety of circuit devices, including inverters, oscillators, logic gates, registers and the like. Such circuit devices may find application in a variety of applications, including integrated circuits, printed circuit boards, flat panel displays, smart cards, cell phones, and RFID tags. In some applications, the ac-powered logic circuitry may eliminate the need for ac-dc rectification components, thereby reducing the manufacturing time, expense, cost, complexity, and size of the component carrying the circuitry.

Claims

1. An electronic circuit comprising:

a first transistor and a second transistor arranged to form a logic gate; and

an alternating current (ac) source to directly power the logic gate with an ac power waveform.

2. The circuit of claim 1, wherein the logic gate includes one of an inverter, a NOR gate, and a NAND gate.

3. The circuit of claim 1, wherein the logic gate forms an analog amplifier.

4. The circuit of claim 1, further comprising a display element, wherein the logic gate is coupled to drive the display element.

5. The circuit of claim 4, wherein the display element includes one of a light emitting diode and a liquid crystal display element.

6. The circuit of claim 1, further comprising a load capacitor coupled to an output of the logic gate.

7. The circuit of claim 6, wherein the logic gate is a first logic gate and the circuit further includes a second logic gate, wherein an output of the first logic gate drives an input of the second logic gate, and wherein the load capacitor is formed at least in part by an input capacitance of the second logic gate.

8. The circuit of claim 1, wherein the circuit includes a series of inverter stages, the inverter stages being coupled to form at least part of a ring oscillator.

9. The circuit of claim 8, further comprising:

a plurality of data lines; and

a plurality of logic gates that selectively output data from the data lines in response to a clock signal generated by the ring oscillator.

10. The circuit of claim 9, wherein the transistors include a plurality of thin film transistors arranged to form at least part of the logic gates.

11. The circuit of claim 1, wherein the ac power waveform has a period less than a propagation delay time of the logic gate.

12. The circuit of claim 1, wherein at least one of the transistors is an organic thin film transistor.

13. The circuit of claim 12, wherein at least one of the transistors is pentacene-based.

14. The circuit of claim 1, wherein at least one of the transistors is amorphous silicon-based.

15. The circuit of claim 1, wherein the logic gate comprises a CMOS logic gate.

16. The circuit of claim 1, wherein the transistors are formed on a flexible substrate.

17. The circuit of claim 1, wherein the logic gate forms part of a radio frequency identification (RFID) tag.

18. The circuit of claim 1, wherein the first transistor is a load transistor and the second transistor is a drive transistor, and wherein a ratio of a gate width to a gate length of the load transistor is greater than or equal to a ratio of a gate width to a gate length of the drive transistor.

19. A method comprising powering a logic gate formed by at least a first transistor and a second transistor with an alternating current (ac) power waveform produced by an alternating current (ac) power source.

20. The method of claim 19, wherein the logic gate includes one of an inverter, a NOR gate, and a NAND gate.

21. The method of claim 20, further comprising operating the logic gate as an analog amplifier.

22. The method of claim 20, further comprising driving a display element with the logic gate.

23. The circuit of claim 22, wherein the display element includes one of a light emitting diode and a liquid crystal display element.

24. The method of claim 19, further comprising coupling a load capacitor to an output of the logic gate.

25. The method of claim 24, wherein the logic gate is a first logic gate, the method comprising driving an input of a second logic gate with an output of the first logic gate, and wherein the load capacitor is formed at least in part by an input capacitance of the second logic gate.

26. The method of claim 19, wherein the logic gate includes a series of inverter stages coupled to form at least part of a ring oscillator.

27. The method of claim 26, further comprising selectively outputting data from a plurality of data lines in response to a clock signal generated by the ring oscillator.

28. The method of claim 27, wherein the transistors include a plurality of thin film transistors arranged to form at least part of the logic gates.

29. The method of claim 19, wherein the ac power waveform has a period less than a propagation delay time of the logic gate.

30. The method of claim 19, wherein at least one of the transistors is an organic thin film transistor.

31. The method of claim 30, wherein at least one of the transistors is pentacene-based.

32. The method of claim 19, wherein at least one of the transistors is amorphous silicon-based.

33. The method of claim 19, wherein the logic gate comprises a CMOS logic gate.

34. The method of claim 19, wherein the transistors are formed on a flexible substrate.

35. The method of claim 19, wherein the logic gate forms part of a radio frequency identification (RFID) tag.

36. The method of claim 19, wherein the first transistor is a load transistor and the second transistor is a drive transistor, and wherein a ratio of a gate width to a gate length of the load transistor is greater than or equal to a ratio of a gate width to a gate length of the drive transistor

37. A radio frequency identification (RFID) tag comprising:

a logic gate formed by at least a first transistor and a second transistor; and

a radio frequency converter that converts RF energy to alternating current (ac) power, and directly powers the logic gate with the ac power.

38. The RFID tag of claim 37, wherein the logic gate includes one of an inverter, a NOR gate, and a NAND gate.

39. The RFID tag of claim 37, wherein the logic gate forms an analog amplifier.

40. The RFID tag of claim 37, further comprising a load capacitor coupled to an output of the logic gate.

41. The RFID tag of claim 40, wherein the logic gate is a first logic gate and the circuit further includes a second logic gate, wherein an output of the first logic gate drives an input of the second logic gate, and wherein the load capacitor is formed at least in part by an input capacitance of the second logic gate.

42. The RFID tag of claim 37, wherein the RFID tag includes a series of inverter stages, the inverter stages being coupled to form at least part of a ring oscillator.

43. The RFID tag of claim 42, further comprising:

a plurality of data lines; and

a plurality of logic gates that selectively output data from the data lines in response to a clock signal generated by the ring oscillator.

44. The RFID tag of claim 43, wherein the transistors include a plurality of thin film transistors arranged to form at least part of the logic gates.

45. The RFID tag of claim 37, wherein the ac power waveform has a period less than a propagation delay time of the logic gate.

46. The RFID tag of claim 37, wherein at least one of the transistors is an organic thin film transistor.

47. The RFID tag of claim 46, wherein at least one of the transistors is pentacene-based.

48. The RFID tag of claim 37, wherein at least one of the transistors is amorphous silicon-based.

49. The RFID tag of claim 37, wherein the logic gate comprises a CMOS logic gate.

50. The RFID tag of claim 37, wherein the transistors are formed on a flexible substrate.

51. The RFID tag of claim 37, wherein the first transistor is a load transistor and the second transistor is a drive transistor, and wherein a ratio of a gate width to a gate length of the load transistor is greater than or equal to a ratio of a gate width to a gate length of the drive transistor.

52. A radio frequency identification (RFID) system comprising:

an RFID tag including first and second transistors arranged to form a logic gate, a radio frequency (RF) converter that converts RF energy to alternating current (ac) power and directly powers the logic gate with the ac power, and a modulator that conveys information; and

an RFID reader that transmits the RF energy to the RFID tag for conversion by the RF converter, and reads the information conveyed by the modulator.

53. The system of claim 52, wherein the logic gate includes one of an inverter, a NOR gate, and a NAND gate.

54. The system of claim 52, wherein the logic gate forms an analog amplifier.

55. The system of claim 52, further comprising a load capacitor coupled to an output of the logic gate.

56. The system of claim 55, wherein the logic gate is a first logic gate and the circuit further includes a second logic gate, wherein an output of the first logic gate drives an input of the second logic gate, and wherein the load capacitor is formed at least in part by an input capacitance of the second logic gate.

57. The system of claim 52, wherein the RFID tag includes a series of inverter stages, the inverter stages being coupled to form at least part of a ring oscillator.

58. The system of claim 57, further comprising:

a plurality of data lines; and

a plurality of logic gates that selectively output data from the data lines in response to a clock signal generated by the ring oscillator.

59. The system of claim 58, wherein the transistors include a plurality of thin film transistors arranged to form at least part of the logic gates.

60. The system of claim 52, wherein the ac power waveform has a period less than a propagation delay time of the logic gate.

61. The system of claim 52, wherein at least one of the transistors is an organic thin film transistor.

62. The system of claim 61, wherein at least one of the transistors is pentacene-based.

63. The system of claim 52, wherein at least one of the transistors is amorphous silicon-based.

64. The system of claim 52, wherein the logic gate comprises a CMOS logic gate.

65. The system of claim 52, wherein the transistors are formed on a flexible substrate.

66. The system of claim 52, wherein the first transistor is a load transistor and the second transistor is a drive transistor, and wherein a ratio of a gate width to a gate length of the load transistor is greater than or equal to a ratio of a gate width to a gate length of the drive transistor.

67. A ring oscillator circuit comprising:

a plurality of transistors arranged to form a series of inverter stages, the inverter stages being coupled to form a ring oscillator; and

an alternating current (ac) source to directly power the inverter stages in the ring oscillator with an ac power waveform.

68. The ring oscillator circuit of claim 67, wherein at least one of the transistors is pentacene-based.

69. The ring oscillator circuit of claim 67, wherein the transistors are formed on a flexible substrate.