Systems and methods for correcting phase locked loop tracking error using feed-forward phase modulation

• US 20040119514A1
• Filed: 12/23/2002
• Published: 06/24/2004
• Est. Priority Date: 12/23/2002
• Status: Active Grant

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Karlquist, Richard K.
• Granted Patent: US 6,831,491 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03C 3/0908 using a phase locked loop
• CPC Class Codes: H03C 3/0991 including calibration means or calibration methods
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Tracking error in phase locked loop (PLL) devices is addressed utilizing feed-forward phase modulation. Specifically, the phase difference of the reference signal and said oscillator signal of a PLL may be determined utilizing a phase detector. The output of the phase detector may be provided to a loop filter to provide feedback to the VCO of the PLL. Additionally, the filtered phase difference may be provided to a suitably calibrated phase modulator to add an amount of phase modulation to the oscillator signal that is approximately equal and opposite to said phase difference to generate a corrected phase output signal.

Claims

1. A device that is operable to provide a corrected phase output signal, said device comprising:

a phase locked loop (PLL) that generates an oscillator signal that is related to a tuning signal; and

a phase modulator that receives said oscillator signal and a phase signal that is indicative of a phase difference between said oscillator signal and an input signal, wherein said phase modulator generates said corrected phase output signal by adding, to said oscillator signal, an amount of phase modulation that is approximately equal and opposite to said phase difference between said oscillator signal and said input signal.

2. The device of claim 1 further comprising:

a first phase detector that generates said phase signal;

a second phase detector that generates a second phase signal that is indicative of a phase difference between said oscillator signal and an input signal; and

a filter that filters said second phase signal to generate said tuning signal.

3. The device of claim 2 wherein first phase detector is a linear phase detector.

4. The device of claim 2 wherein said second phase detector is a nonlinear phase detector.

5. The device of claim 1 wherein said phase modulator is an Armstrong phase modulator.

6. The device of claim 1 further comprising:

a calibration source that is operable to generate a calibration signal of a frequency that is greater than a bandwidth of said PLL when said device is operated in a calibration mode; and

an adder that combines said calibration signal with said filtered phase signal to drive a voltage controlled oscillator (VCO) of said PLL during said calibration mode.

7. The device of claim 1 further comprising:

a first frequency converter that down-shifts a frequency of said oscillator signal before said oscillator signal is received by said phase modulator.

8. The device of claim 7 further comprising:

a second frequency converter that up-shifts a frequency of said corrected phase output signal.

9. The device of claim 1 further comprising:

a frequency to voltage converter that generates a voltage signal in response to a frequency of said corrected phase output signal.

10. A phase locked loop (PLL) device that is operable to provide a corrected phase output signal, said PLL device comprising:

a voltage controlled oscillator (VCO) that produces an oscillator signal that is related to a tuning signal;

a phase detector that generates a phase signal from an input signal and said oscillator signal; and

a phase modulator that receives said oscillator signal and said phase signal, wherein said phase modulator generates said corrected phase output signal by adding, to said oscillator signal, an amount of phase modulation that is approximately equal and opposite to a phase difference between said input signal and said oscillator signal.

11. The PLL device of claim 10 wherein said phase detector is a linear phase detector.

12. The PLL device of claim 11 further comprising:

a nonlinear phase detector that generates a second phase signal; and

a filter that filters said second phase signal to generate said tuning signal.

13. The PLL device of claim 10 wherein said phase modulator is an Armstrong phase modulator.

14. The PLL device of claim 10 further comprising:

a calibration source that is operable to generate a calibration signal of a frequency that is greater than a PLL bandwidth of the PLL device when said PLL device is operated in a calibration mode; and

an adder that combines said calibration signal with said filtered phase signal to drive said VCO during said calibration mode.

15. The PLL device of claim 10 further comprising:

a first frequency converter that down-shifts a frequency of said oscillator signal before said oscillator signal is received by said phase modulator.

16. The PLL device of claim 15 further comprising:

a second frequency converter that up-shifts a frequency of said corrected phase output signal.

17. The PLL device of claim 10 further comprising:

a frequency to voltage converter that generates a voltage signal in response to a frequency of said corrected phase output signal.

18. A method of providing a corrected phase output signal, comprising:

operating a phase locked loop (PLL) to provide an oscillator signal, wherein said operating includes generating a phase signal that is indicative of a phase difference between said oscillator signal and an input signal; and

utilizing said phase signal to phase modulate said oscillator signal by adding, to said oscillator signal, an amount of phase modulation that is approximately equal and opposite to said phase difference to generate said corrected phase output signal.

19. The method of claim 18 wherein said generating a phase signal is performed by a clock data recovery circuit.

20. The method of claim 18 further comprising:

down-converting said oscillator signal before phase modulating said oscillator signal.

21. The method of claim 18 further comprising:

converting a frequency of said corrected phase output signal to a voltage signal.

22. The method of claim 18 further comprising:

operating said PLL in a calibration mode, wherein said operating includes generating a calibration signal of a frequency that is greater than a loop bandwidth of said PLL, combining said calibration signal with a filtered phase signal of said PLL to produce a combined signal, and using said combined signal to provide a tuning signal to a voltage controlled oscillator (VCO) of said PLL.

23. The method of claim 22 further comprising:

adjusting a gain parameter of said phase modulator.

24. The method of claim 18 wherein said generating a phase signal is performed by a linear phase detector.

25. The method of claim 24 further comprising:

generating a second phase signal that is indicative of a phase difference between said oscillator signal and said input signal with a nonlinear phase detector;

filtering said second phase signal; and

providing said second phase signal as a tuning signal to generate said oscillator signal.

26. A system for providing a recovered clock from a data stream, comprising:

a phase locked loop (PLL) that generates an oscillator signal that is related to a tuning signal;

a first low-pass filter that is operable to filter a reference signal from said PLL that is indicative of a data transition;

a second low-pass filter that is operable to filter a phase signal, from said PLL, that is indicative of a phase difference between said oscillator signal and an input signal;

a phase shifter that is operable to shift a phase of said oscillator signal by 90°

;

an amplitude modulator that modulates said phase shifted oscillator signal with said filtered reference signal to generate a first modulated signal;

a balanced modulator that modulates said oscillator signal by said filtered phase signal to generate a second modulated signal; and

an adder that combines said first modulated signal with said second modulated signal.

27. The system of claim 26 further comprising:

a limiter that is operable to limit an output signal from said adder.

28. The system of claim 26 wherein said data stream is communicated according to a unit interval and a maximum run length of consecutive symbols that occur without a transition, and wherein said first low-pass filter and said second low-pass filter possess a bandwidth that approximately equals one half of the reciprocal of:

said unit interval multiplied by said maximum run length.

29. The system of claim 26 further comprising:

a phase demodulator element that is operable to provide a phase demodulated signal utilizing an output signal from said adder.

30. The system of claim 26 further comprising:

a frequency to voltage converter that is operable to provide a frequency demodulated signal utilizing an output signal from said adder.