Adaptive frequency clock signal

• US 20040119521A1
• Filed: 12/20/2002
• Published: 06/24/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Kurd, Nasser A., Barkatullah, Javed S.
• Granted Patent: US 6,922,111 B2
• Time in Patent Office: Days
• US Class Current: 327/291
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

According to some embodiments, a clock signal having an adaptive frequency is provided.

Claims

1. A circuit, comprising:

a clock signal input line to receive an input clock signal; and

a clock signal output line to provide an output clock signal having an adjusted frequency that is based on a condition associated with a die.

2. The circuit of claim 1, wherein the output clock signal is synchronized with the input clock signal.

3. The circuit of claim 1, wherein the output clock signal has a default frequency when the condition is not present and the adjusted frequency when the condition is present.

4. The circuit of claim 3, wherein the adjusted frequency is one of a plurality of discrete values.

5. The circuit of claim 1, further comprising:

a phase-locked loop unit coupled to the clock signal input line.

6. The circuit of claim 5, further comprising:

a plurality of core state elements coupled to the clock signal output line via a core clock network.

7. The circuit of claim 6, further comprising:

a first-in, first-out storage structure to exchange information with at least some of the core state elements.

8. The circuit of claim 7, wherein the first-in, first-out storage structure comprises a circular buffer circuit including a multiplexer.

9. The circuit of claim 7, wherein the first-in, first-out storage structure is also to exchange information with at least some of a plurality of input output state elements.

10. The circuit of claim 6, further comprising:

a matched core clock network coupled to;

(i) the phase-locked loop unit via a divider, and (ii) the clock signal input line.

11. The circuit of claim 1, further comprising:

a detector to detect the condition.

12. The circuit of claim 11, wherein the detector comprises at least one of:

(i) a voltage droop detector, and (ii) a thermal detector.

13. The circuit of claim 11, wherein the detector determines a level associated with the condition in accordance with a plurality of pre-determined threshold values.

14. The circuit of claim 1, further comprising:

a delay chain to generate the output clock signal.

15. The circuit of claim 14, wherein the delay chain comprises a plurality of bimodal delay elements.

16. The circuit of claim 14, wherein the adjusted frequency comprises one of a plurality of reduced values or at least one compensating value.

17. The circuit of claim 1, further comprising:

a delay-locked loop unit coupled to the clock signal input line and adapted to generate a plurality of offset clock signals.

18. The circuit of claim 17, further comprising:

a multiplexer to receive the plurality of offset clock signals.

19. The circuit of claim 18, further comprising:

a select state machine coupled to the multiplexer and adapted to select one of the offset clock signals to create the output clock signal.

20. The circuit of claim 19, further comprising:

a detector to provide a condition detect signal to the select state machine, wherein the select state machine selects one of the offset clock signals in accordance with the condition detect signal.

21. The circuit of claim 20, further comprising:

a meta-stable immune interface between the detector and the select state machine, wherein the meta-stable immune interface is to facilitate generation of the output clock signal at the adjusted frequency until an asynchronous condition signal becomes synchronized.

22. The circuit of claim 20, further comprising:

a mode select state machine coupled to the detector and the select state machine.

23. The circuit of claim 22, wherein the mode select state machine comprises:

a counter.

24. The circuit of claim 23, wherein the output clock signal has a default frequency higher than the adjusted frequency, and the counter is to arrange for the output clock signal to have another frequency higher than the default frequency when the condition is no longer present.

25. The circuit of claim 18, further comprising:

a delay chain coupled between the multiplexer and the clock signal output line.

26. The circuit of claim 18, further comprising:

a clock scrambler coupled between the delay-locked loop unit and the multiplexer, wherein the clock scrambler is to arrange the offset clock signals in an order associated with the adjusted frequency.

27. The circuit of claim 17, wherein the delay-locked loop unit is to generate:

(i) a first set of offset clock signals based on the input clock signal, and (ii) the plurality of offset clock signals are generated based on an interpolation of the first set of offset clock signals.

28. The circuit of claim 27, wherein the interpolation is performed via at least one of:

(i) buffer sizing, and (ii) tap shorting.

29. The circuit of claim 17, wherein the delay-locked loop unit comprises:

a phase detector coupled to the clock signal input line;

a charge pump coupled to the phase detector;

a capacitor coupled between the charge pump and a ground;

a bias unit coupled to the charge pump;

a delay chain coupled to the bias circuitry, the clock signal input line, and the phase detector; and

a clock interpolator.

30. The circuit of claim 1, wherein the input clock signal comprises a reference clock signal and the frequency of the output clock signal is adjusted in an analog fashion.

31. The circuit of claim 30, further comprising:

a core voltage tracking phase-locked loop unit coupled to the clock signal input line and the clock signal output line.

32. The circuit of claim 31, further comprising:

a digital power supply to provide power to the core voltage tracking phase-locked loop unit.

33. The circuit of claim 32, wherein the core voltage tracking phase-locked loop unit further comprises a high frequency filter.

34. The circuit of claim 33, further comprising a charge pump having an adjustable strength.

35. The circuit of claim 31, wherein a phase frequency detect signal is disabled during a voltage droop and is held for a at least one cycle after the voltage droop is no longer present.

36. A method, comprising:

determining a condition associated with a die; and

adjusting a frequency of a clock signal based on the determined condition.

37. The method of claim 36, wherein the condition is associated with a voltage provided to state elements.

38. The method of claim 36, wherein the condition is associated with a temperature of the die.

39. The method of claim 36, wherein said determining comprises determining a level associated with the condition and the frequency is adjusted based on the level.

40. The method of claim 36, wherein the clock signal originally had a default frequency, said adjusting comprises adjusting the frequency to an adjusted frequency, and further comprising:

determining that the condition is no longer present; and

adjusting the frequency to a compensating frequency.

41. The method of claim 36, wherein the adjusted frequency is lower than the default frequency and the compensating frequency is higher than the default frequency.

42. The method of claim 41, wherein the difference between the default and adjusted frequencies is greater than the difference between the default and compensating frequencies.

43. The method of claim 41, wherein the clock frequency remains at the compensating frequency longer than it remained at the adjusted frequency.

44. The method of claim 43, further comprising:

adjusting the frequency back to the default frequency.

45. The method of claim 36, wherein the frequency is adjusted to one of a plurality of discrete frequencies.

46. The method of claim 45, wherein the frequency is adjusted via a delay chain.

47. The method of claim 45, wherein the frequency is adjusted via a delay-locked loop unit and a state machine.

48. The method of claim 36, further comprising:

generating a plurality of offset clock signals; and

selecting edges from the plurality of offset clock signals to generate the clock signal with the adjusted frequency.

49. The method of claim 36, wherein the frequency is adjusted in an analog fashion.

50. The method of claim 49, wherein the frequency is adjusted by a core voltage tracking phase-locked loop unit.

51. The method of claim 50, wherein a digital power supply provides power to the core voltage tracking phase-locked loop unit.

52. The method of claim 51, wherein the core voltage tracking phase-locked loop unit includes a high frequency filter.

53. A processor, comprising:

a core portion adapted to generate a core clock signal having an adjusted frequency that is based on a condition associated with a die;

an input output portion adapted to generate an input output clock signal having a fixed frequency; and

a storage structure between the core portion and the input output portion.

54. The processor of claim 53, wherein the adjusted frequency is one of a plurality of discrete values.

55. The processor of claim 53, wherein the frequency is adjusted in an analog fashion.

56. A system, comprising:

a chipset; and

a die comprising a microprocessor in communication with the chipset, wherein the microprocessor includes an adaptive frequency system comprising;

a clock signal input line to receive an input clock signal; and

a clock signal output line to provide an output clock signal having an adjusted frequency that is based on a condition associated with a die.

57. The system of claim 56, wherein the adjusted frequency is one of a plurality of discrete values.

58. The system of claim 56, wherein the input clock signal comprises a reference clock signal and the frequency of the output clock signal is adjusted in an analog fashion.