SYSTEM AND METHOD FOR DESIGNING AND USING ANALOG CIRCUITS OPERATING IN THE MODULATION DOMAIN

• US 20040119622A1
• Filed: 12/23/2002
• Published: 06/24/2004
• Est. Priority Date: 12/23/2002
• Status: Active Grant

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Karlquist, Richard K.
• Granted Patent: US 6,765,519 B2
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: G06G 7/16 for multiplication or division G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00

Abstract

There is disclosed a computation circuit, working in the modulation domain to generate a signal having phase modulation proportional to the ratio of the dividend (numerator) signal to the divisor (denominator) signal. In one embodiment, the phase modulated signal is demodulated by a phase demodulator to produce a baseband quotient signal. The divisor signal maintains inverse proportional control of the modulation gain of the modulator by varying the carrier injection level, resulting in higher bandwidth and accuracy, and lower drift and offset compared to traditional analog computation techniques. In one embodiment the circuit contains all linear components, even though the division function is a non-linear function. The circuit and method operate when the input signals are analog or one or both are in the modulation domain.

Claims

1. A circuit for providing an output signal that is the ratio of two input signals, said circuit comprising:

means for providing a first signal having a phase modulation index proportional to the ratio of one input signal to the other input signal.

2. The circuit of claim 1 further comprising:

means for phase demodulating said signal to provide an output signal as a baseband signal.

3. The circuit of claim 2 wherein said providing means is an Armstrong phase modulator modified to have its modulation sensitivity controllable.

4. The circuit of claim 2 wherein said first signal may include amplitude modulation and wherein said circuit further includes:

means for removing any said amplitude modulation from said first signal.

5. The circuit of claim 4 wherein said removing means is a limiter inserted ahead of said phase demodulating means.

6. The circuit of claim 1 wherein said providing means includes a vector modulator having cartesian inputs.

7. The circuit of claim 1 wherein said providing means includes an I/Q modulator where the Q input receives the dividend input signal and wherein the I input receives the divisor input and the LO input receives a carrier source input.

8. The circuit of claim 1 wherein said providing means includes an I/Q modulator where the I input receives the dividend input signal and wherein the Q input receives the divisor input and the LO input receives a carrier source input.

9. The circuit of claim 1 wherein said phase demodulating means receives as one input said first signal and receives as a second input a non-phase shifted amplified carrier signal.

10. The circuit of claim 9 wherein said phase demodulator means is a multiplier.

11. The circuit of claim 10 wherein said multiplier is low pass filtered.

12. A circuit for dividing a first analog signal by a second analog signal, said circuit comprising:

a double side band suppressed carrier modulator for accepting said first analog signal and for accepting a sine wave carrier signal;

an amplitude modulator for accepting said second analog signal and for accepting a phase shifted carrier signal;

an adder for combining the outputs of said double side band suppressed carrier modulator and said amplitude modulator; and

a phase demodulator for accepting said carrier signal and for accepting the output of said adder, said phase demodulator providing, as an output, a signal which is said first signal divided by said second signal.

13. The circuit of claim 12 wherein at least one of said double side band suppressed carrier modulator, said amplitude modulator and said phase modulator is a multiplier circuit.

14. The circuit of claim 12 further including:

a limiter for accepting the output from said adder prior to said output being supplied to said phase modulator.

15. A method of processing a pair of input signals, said method comprising:

adding together a first signal comprised of a first one of said input signals modulated by a sine wave carrier and a second signal comprised of said second one of said input signals modulated by a cosine wave carrier; and

phase demodulating the output of said added together signals.

16. The method of claim 15 further comprising:

stripping out the amplitude modulation after said adding step.

17. A method of processing a pair of input signals, said method comprising:

modulating a carrier signal by a first one of said input signals;

modulating a phase shifted carrier signal by a second one of said input signals;

adding together said first and second modulated signals; and

phase demodulating the output of said adding step.

18. The method of claim 17 further comprising:

stripping out the amplitude modulation from said adding step.

19. A circuit for processing input signals;

said circuit comprising;

a first multiplier having one input for accepting one of said input signals and a second input for accepting a sine wave carrier signal;

a second multiplier having one input for accepting a second one of said input signals and a second input for accepting a signal which has been phase shifted from said sine wave carrier;

an adder for adding the outputs of said multipliers to provide an added output signal; and

a third multiplier having one input for accepting said added output signal, a second input for accepting said sine wave carrier signal so as to provide an output signal which is the quotient of said first signal divided by said second signal.

20. The circuit of claim 19 further comprising:

a limiter for stripping off at least a portion of the amplitude modulation of said added output signal.

21. A method of processing a pair of input signals, said method comprising:

modulating a carrier signal by a first one of said input signals;

phase shifting a modulation domain second input signal; and

adding together said first input modulated signal and said phase shifted second input signal to provide a quotient output signal as a modulated output signal.

22. The method of claim 21 further comprising:

phase demodulating said quotient output signal.

23. The method of claim 21 further comprising:

stripping out any amplitude modulation from said quotient output signal.

24. The method of claim 21 further comprising:

filtering certain frequencies from said quotient output signal.

25. A method of processing a pair of input signals, said method comprising:

providing a modulation domain input signal to an adder;

modulating a phase shifted carrier signal by a second one of said input signals and providing said modulated signal to said adder to provide a quotient output signal as a modulated signal.

26. The method of claim 25 further comprising:

phase demodulating said modulated quotient output signal.

27. The method of claim 25 further comprising:

stripping out any amplitude modulation from said quotient output signal.