Current sense amplifier

• US 20040120200A1
• Filed: 12/20/2002
• Published: 06/24/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, Adesto Technologies Corporation (Renesas Electronics Corporation)
• Original Assignee: Infineon Technologies AG
• Inventors: Gogl, Dietmar, Reohr, William Robert, DeBrosse, John Kenneth
• Granted Patent: US 6,946,882 B2
• Time in Patent Office: Days
• US Class Current: 365/210
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

Claims

1. A current sense amplifier, comprising:

a voltage comparator having a first input, a second input and an output;

a first clamping device coupled between the first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage;

a second clamping device coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage; and

a configurable load device coupled between the first and second input of the voltage comparator.

2. The current sense amplifier according to claim 1, wherein the configurable load device comprises a configurable current mirror.

3. The current sense amplifier according to claim 2, wherein the configurable current mirror comprises:

a first transistor coupled between a voltage source and the first clamping device;

a second transistor coupled between the voltage source and the second clamping device, the first and second transistor gates being coupled together;

a first switching transistor coupled between the first transistor gate and drain; and

a second switching transistor coupled between the second transistor gate and drain, wherein either the first transistor or second transistor may be used as a transistor diode or a current source.

4. The current sense amplifier according to claim 3, wherein a first select signal is coupled to the first switching transistor gate, and the inverse of the first select signal is coupled to the second switching transistor gate, wherein the first select signal is adapted to activate either the first switching transistor or the second switching transistor, activating either the first transistor as a transistor diode and the second transistor as a current source, or vice versa, thus amplifying the voltage difference at the first and second input of the voltage comparator.

5. The current sense amplifier according to claim 1, wherein the first clamping device comprises a third transistor having gate, source and a drain;

wherein the gate of the third transistor is coupled to the reference voltage;

wherein the source of the third transistor is coupled to the first input signal;

wherein the drain of the third transistor is coupled to the first input of the voltage comparator;

wherein the second clamping device comprises a fourth transistor having gate, source and a drain;

wherein the gate of the fourth transistor is coupled to the reference voltage;

wherein the source of the fourth transistor is coupled to the second input signal; and

wherein the drain of the fourth transistor is coupled to the second input of the voltage comparator.

6. The current sense amplifier according to claim 1, further comprising a first equalizing transistor coupled between the inputs of the voltage comparator, and a second equalizing transistor coupled between the first input signal and the second input signal.

7. The current sense amplifier according to claim 1, further comprising:

a first cascode device coupled between the configurable load device and the first clamping device; and

a second cascode device coupled between the configurable load device and the second clamping device.

8. The current sense amplifier according to claim 1, wherein the first input signal comprises a current from a selected memory cell being read, wherein the second input signal comprises a reference current of at least one reference cell, and wherein the voltage comparator outputs a logic state of the selected memory cell.

9. The current sense amplifier according to claim 8, wherein the reference current comprises the averaged current from at least two reference cells.

10. The current sense amplifier according to claim 4, further comprising a configurable dummy load circuit coupled to the configurable current mirror.

11. The current sense amplifier according to claim 10, wherein the configurable dummy load circuit comprises:

a first dummy transistor coupled between the voltage source and the first transistor of the current mirror;

a second dummy transistor coupled between the voltage source and the second transistor of the current mirror, wherein the gate of the second dummy transistor is coupled to the gate of the first dummy transistor;

a first dummy select transistor coupled between the first transistor of the current mirror and the gate of the first dummy transistor, the gate of the first dummy select transistor being coupled to the inverse of the first select signal; and

a second dummy select transistor coupled between the second transistor of the current mirror and the gate of the second dummy transistor, the gate of the second dummy select transistor being coupled to the first select signal.

12. A current sensing circuit, comprising:

a first current sense amplifier according to claim 3;

a second current sense amplifier according to claim 3;

a first connection transistor coupled between the first transistors of the first and second current sense amplifiers; and

a second connection transistor coupled between the second transistors of the first and second current sense amplifiers.

13. The current sensing circuit according to claim 12, wherein the circuit comprises a symmetric sensing scheme.

14. A current sense amplifier, comprising:

a voltage comparator having a first input, a second input and an output;

a first clamping device coupled between the first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage;

a second clamping device coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage;

a load device having a first side and a second side; and

a multiplexer, wherein the multiplexer is adapted to select whether the first input signal or second input signal is connected to the first or second side of the load device.

15. The current sense amplifier according to claim 14, wherein the load device comprises a current mirror, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, the first and second transistor gates being coupled together, the gate and drain of the second transistor being coupled together.

16. The current sense amplifier according to claim 14, wherein the multiplexer is coupled between the first input signal and the first clamping device, and between the second input signal and the second clamping device.

17. The current sense amplifier according to claim 14, wherein the multiplexer is coupled between the first clamping device, the first input of the voltage comparator and the load device, and between the second clamping device, the second input of the voltage comparator and the load device.

18. The current sense amplifier according to claim 14, wherein the multiplexer comprises the first clamping device and the second clamping device.

19. The current sense amplifier according to claim 18, wherein the first clamping device comprises a third transistor and a fourth transistor, wherein a first analog signal is coupled to the gate of the third transistor and a second analog signal is coupled to the gate of the fourth transistor, wherein the second clamping device comprises a fifth transistor and a sixth transistor, wherein the first analog signal is coupled to the gate of the fifth transistor and the second analog signal is coupled to the gate of the sixth transistor, wherein the first and second analog signals select whether the first input signal or second input signal is connected to the first or second side of the load device.

20. The current sense amplifier according to claim 14, further comprising a first equalizing transistor coupled between the inputs of the voltage comparator, and a second equalizing transistor coupled between the first input signal and the second input signal.

21. The current sense amplifier according to claim 15, further comprising at least one capacitive device coupled across the drain and source of the first transistor of the current mirror, wherein the at least one capacitor is adapted to balance capacitive loads of the current mirror.

22. The current sense amplifier according to claim 14, wherein the first input signal comprises a current from a selected memory cell being read, wherein the second input signal comprises a current from at least one reference cell, and wherein the voltage comparator outputs a logic state of the selected memory cell.

23. The current sense amplifier according to claim 22, wherein the reference current comprises the averaged current from at least two reference cells.

24. A current sensing circuit, comprising:

a first current sense amplifier according to claim 15;

and

a second current sense amplifier according to claim 15, wherein the first and second current sense amplifiers are connected at the second transistors of the current mirrors of the first and second current sense amplifiers.

25. The current sensing circuit according to claim 24, wherein the first and second current sense amplifiers are connected at the second clamping devices of the first and second current sense amplifiers.

26. The current sensing circuit according to claim 24, wherein the circuit comprises a symmetric sensing scheme.

27. A memory device, comprising:

an array of memory cells, the memory cells having a first side and a second side, wherein at least two of the memory cells comprise reference cells;

a plurality of parallel wordlines coupled proximate the first side of the memory cells, the wordlines running in a first direction;

a plurality of parallel bitlines coupled proximate the second side of the memory cells; and

a symmetric sensing circuit including at least one column selector and at least one current sense amplifier, the at least one column selector being coupled to the memory array and comprising at least one column select transistor coupled to each bitline in the array, the at least one current sense amplifier including a voltage comparator, a first clamping device, a second clamping device, and a current mirror having a first side and a second side, wherein the voltage comparator includes a first input, a second input and an output, wherein a first input signal is coupled to the voltage comparator first input, wherein a second input signal is coupled to the voltage comparator second input, the first and second input signals comprising either current from a selected memory cell or current from at least one reference cell, and wherein the voltage comparator outputs a logic state of the selected memory cell.

28. The current sense amplifier according to claim 27, wherein the current from at least one reference cell comprises the averaged current from at least two reference cells.

29. The memory device according to claim 27, wherein the first clamping device is coupled between the first input of the voltage comparator and the first input signal, the first clamping device being coupled to a reference voltage, wherein the second clamping device is coupled between the second input of the voltage comparator and the second input signal, the second clamping device being coupled to the reference voltage, wherein the current mirror is configurable and is coupled between the first and second input of the voltage comparator, wherein either the first or second side of the current mirror may be selected.

30. The memory device according to claim 29, wherein the current sense amplifier configurable current mirror comprises:

a first transistor coupled between a voltage source and the first clamping device;

a second transistor coupled between the voltage source and the second clamping device, the first and second transistor gates-being coupled together;

a first switching transistor coupled between the first transistor gate and drain, a first select signal being coupled to the first switching transistor gate; and

a second switching transistor coupled between the second transistor gate and drain, the inverse of the first select signal being coupled to the second switching transistor gate, wherein the first select signal is adapted to activate either the first switching transistor or the second switching transistor, activating either the first transistor or second transistor as a transistor diode or a current source, amplifying the voltage difference at the first and second input of the voltage comparator.

31. The memory device according to claim 29, wherein the current sense amplifier further comprises:

a first cascode device coupled between the configurable current mirror and the first clamping device; and

a second cascode device coupled between the configurable current mirror and the second clamping device.

32. The memory device according to claim 29, wherein the current sense amplifier further comprises a configurable dummy load circuit coupled to the configurable current mirror.

33. The memory device according to claim 32, wherein the configurable dummy load circuit comprises:

a first dummy transistor coupled between the voltage source and the first transistor of the current mirror;

a second dummy transistor coupled between the voltage source and the-second transistor of the current mirror, wherein the gate of the second dummy transistor is coupled to the gate of the first dummy transistor;

a first dummy select transistor coupled between the first transistor of the current mirror and the gate of the first dummy transistor, the gate of the first dummy select transistor being coupled to the inverse of the first select signal; and

a second dummy select transistor coupled between the second transistor of the current mirror and the gate of the second dummy transistor, the gate of the second dummy select transistor being coupled to the first select signal.

34. The memory device according to claim 27, wherein the current mirror first side includes a first transistor coupled between a voltage source and the first clamping device, the current mirror second side includes a second transistor coupled between the voltage source and the second clamping device, the first and second transistor gates being coupled together, and the gate and drain of the second transistor being coupled together, wherein the symmetric sensing circuit further comprises a multiplexer, wherein the multiplexer is adapted to select whether the first input signal or second input signal is connected to first or second side of the current mirror.

35. The memory device according to claim 34, wherein the multiplexer is coupled between the first input signal and the first clamping device, and between the second input signal and the second clamping device.

36. The memory device according to claim 34, wherein the multiplexer is coupled between the first clamping device, the first input of the voltage comparator and the current mirror, and between the second clamping device, the second input of the voltage comparator and the current mirror.

37. The memory device according to claim 34, wherein the multiplexer comprises the first clamping device and the second clamping device.

38. The memory device according to claim 37, wherein the first clamping device comprises a third transistor and a fourth transistor, wherein a first analog signal is coupled to the gate of the third transistor and a second analog signal is coupled to the gate of the fourth transistor, wherein the second clamping device comprises a fifth transistor and a sixth transistor, wherein the first analog signal is coupled to the gate of the fifth transistor and the second analog signal is coupled to the gate of the sixth transistor, wherein the first and second analog signals select whether the first input signal or second input signal is connected to first or second side of the current mirror.

39. The memory device according to claim 34, wherein the current sense amplifier further comprises:

at least one capacitive device coupled across the drain and source of the first transistor of the current mirror, wherein the capacitor is adapted to balance capacitive loads of the current mirror.

40. The memory device according to claim 27, wherein the current sense amplifier further comprises:

a first equalizing transistor coupled between the first input and second input of the voltage comparator; and

a second equalizing transistor coupled between the first input signal and the second input signal.

41. The memory device according to claim 27, wherein the symmetric sensing circuit comprises exactly two current sense amplifiers, and wherein the two current sense amplifiers are coupled together at the first or second transistors of the current mirrors of the two current sense amplifiers.

42. The memory device according to claim 27, wherein the memory cells comprise magnetic tunnel junctions, wherein the memory device comprises a magnetic random access memory (MRAM) device.

43. A method of sensing current, comprising:

providing a first transistor and a second transistor;

providing a first input signal having a first voltage and a first current;

clamping the first voltage and passing the first current to the first transistor;

providing a second input signal having a second voltage and a second current;

clamping the second voltage and passing the second current to the second transistor, wherein the first input signal and second input signal comprise either current from a selected memory cell or current from at least one reference cell;

selectively mirroring the first or second current from the first or second transistor to the second or first transistor; and

comparing the voltage across the first or second transistor to the voltage across the second or first transistor, wherein selectively mirroring the current amplifies the voltage difference between the voltage across the first transistor and the voltage across the second transistor.

44. The method according to claim 43, wherein the first transistor and second transistor voltage difference indicates a resistive state of the selected memory cell.

45. The method according to claim 43, wherein the memory device comprises a symmetric sensing architecture, wherein the sensing current method is symmetric.

46. The method according to claim 43, wherein the selective mirroring is by a configurable current mirror.

47. The method according to claim 43, wherein the selective mirroring is by multiplexing devices.