Composite memory device
First Claim
1. A composite memory device, comprising:
- a first asynchronous memory device;
a second synchronous memory device configured to operate in a page mode;
a third synchronous memory device configured to operate in a burst mode;
a memory bus configured to transfer data among the first through the third memory devices;
a first memory controller configured to control data transfer operation between the first memory device and the memory bus;
a second memory controller configured to control data transfer operation between the second memory device and the memory bus; and
a third memory controller configured to control data transfer operation between the third memory device and the memory bus, wherein the first through the third memory devices are controlled by an external memory controller to exchange data with an external system bus, and when one of the first through the third memory devices exchanges data with the external system bus, the rest two memory devices are allowed to exchange data via the memory bus.
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Abstract
The present invention relates to a composite memory device comprising first through third memory devices, a memory bus, and first through third memory controllers. The first memory device is an asynchronous memory device, the second memory device is a synchronous memory device configured to operate in a page mode, and the third memory device is a synchronous memory device configured to operate in a burst mode. The first through the third memory controllers are configured to control data transfer operation between the memory bus and the first through the third memory devices, respectively. The first through the third memory devices are controlled by an external memory controller to exchange data with an external system bus, and when one of the first through the third memory devices exchanges data with the external system bus, the rest two memory devices are allowed to exchange data via the memory bus.
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Citations
15 Claims
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1. A composite memory device, comprising:
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a first asynchronous memory device;
a second synchronous memory device configured to operate in a page mode;
a third synchronous memory device configured to operate in a burst mode;
a memory bus configured to transfer data among the first through the third memory devices;
a first memory controller configured to control data transfer operation between the first memory device and the memory bus;
a second memory controller configured to control data transfer operation between the second memory device and the memory bus; and
a third memory controller configured to control data transfer operation between the third memory device and the memory bus, wherein the first through the third memory devices are controlled by an external memory controller to exchange data with an external system bus, and when one of the first through the third memory devices exchanges data with the external system bus, the rest two memory devices are allowed to exchange data via the memory bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A composite memory device, comprising:
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a plurality of memory devices configured to operate individually;
a memory bus configured to transfer data among the plurality of memory devices; and
a plurality of memory controllers configured to control data transfer operation between the memory bus and a memory device among the plurality of the memory devices respectively, wherein the plurality of memory devices are controlled by an external memory controller to exchange data with an external system bus, and when one of the plurality of memory devices exchanges data with the external system bus, the rest memory devices are allowed to exchange data via the memory bus.
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Specification