Integrated circuit for code acquisition

• US 20040120385A1
• Filed: 08/01/2003
• Published: 06/24/2004
• Est. Priority Date: 08/02/2002
• Status: Active Application

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV), STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Mattos, Philip, Losi, Marco
• Granted Patent: US 7,406,113 B2
• Time in Patent Office: Days
• US Class Current: 375/148
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
• CPC Class Codes: H04B 1/70753 Partial phase search
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators without sample reduction. The same correlators are thereby used to increase acquisition speed.

Claims

1. A semiconductor integrated circuit for processing a plurality of received broadcast signals, the broadcast signals being of the type each having a different respective known digital code, the semiconductor integrated circuit comprising:

a digital sampler;

a sample reducer; and

a plurality of correlators being arranged to be operable in two modes wherein;

in an acquisition mode;

the digital sampler samples the received broadcast signals to produce a digital bit stream at a first bit rate;

the sample reducer reduces bits of the digital bit stream by combining groups of N bits together to produce a reduced digital bit stream;

the plurality of correlators receive the reduced digital bit stream at a second bit rate, being higher than the first bit rate, and each of the plurality of correlators correlates the reduced digital bit stream with a same locally generated version of one of the different known digital codes; and

in a tracking mode;

the digital sampler samples the received broadcast signals to produce a digital bit stream at the first bit rate and provides that digital bit stream direct to each of the plurality of correlators, each correlator correlates that digital bit stream with a different locally generated version of one of the known digital codes.

2. A semiconductor integrated circuit according to claim 1 wherein in acquisition mode the sample reducer comprises an adder to add the groups of N bits.

3. A semiconductor integrated circuit according to claim 2 wherein in acquisition mode the adder provides a digital output representative of a value of a sum of the N bits.

4. A semiconductor integrated circuit according to claim 3 wherein in acquisition mode the adder provides a logic “

1”

output if the sum of the N bits is greater than a given value and a logic “

0”

output if the sum of N bits is less than the given value.

5. A semiconductor integrated circuit according to claim 4 wherein in acquisition mode the adder alternately provides a logic “

1” and

logic “

0”

if the sum of the N bits is equal to the given value.

6. A semiconductor integrated circuit according to claim 1 wherein in acquisition mode the second bit rate is a factor M higher than the first bit rate.

7. A semiconductor integrated circuit according to claim 6 wherein there are Y correlators such that in acquisition mode a correlation rate is a factor X=N (bits)×

M (bit rate factor)×

Y(correlators) faster than a correlation rate in tracking mode for one of the known digital codes.

8. A semiconductor integrated circuit according to claim 7 wherein the factor X is chosen to be substantially equal or greater than twice a number of bits in the known code, wherein all possible correlations of the code are performed before the code repeats.

9. A semiconductor integrated circuit according to claim 8 wherein the known digital code is a GPS position code of 1,023 bits and wherein the factor X is arranged to be 2,048.

10. A semiconductor integrated circuit according to claim 1, further comprising a memory to receive the reduced digital bit stream and to output the reduced digital bit stream at the second bit rate to the plurality of correlators.

11. A semiconductor integrated circuit according to claim 10 wherein the memory comprises a circulating shift register.

12. A semiconductor integrated circuit according to claim 11 wherein the circulating shift register receives the reduced digital bit stream at a rate equal to the first bit rate divided by N and circulates at the second bit rate.

13. A semiconductor integrated circuit according to claim 10 wherein the memory comprises two shift registers arranged to alternately receive the reduced digital bit stream while another of the two shift registers circulates at the second bit rate.

14. A method of processing a plurality of received broadcast signals each having a different respective known digital code, the method comprising:

sampling the received broadcast signals to produce a digital bit stream at a first bit rate;

reducing bits of the digital bit stream by combining groups of N bits to produce a reduced bit stream;

correlating the reduced digital bit stream at a second bit rate using a plurality of correlators each correlating the reduced digital bit stream with a same one of a locally generated version of the known digital codes to acquire the broadcast signals; and

subsequently correlating the digital bit stream at the first bit rate using the plurality of correlators each correlating the reduced digital bit stream with a locally generated version of a different one of the known digital codes to track the previously acquired signals.

15. A method according to claim 14 wherein the reducing the bits of the digital bit stream comprises summing groups of N bits.

16. A method according to claim 15 wherein the summing produces a digital output representative of the sum.

17. A method according to claim 16 wherein the summing produces a logic “

1”

if the sum of N bits is greater than a given value and a logic “

0”

if the sum is less than the given value.

18. A method according to claim 17 wherein the summing alternately provides a logic “

1” and

logic “

0”

if the sum of N bits is equal to the given value.

19. A method according to claim 14 wherein the second bit rate is a factor M higher than the first bit rate.

20. A method according to claim 19 wherein there are Y correlators such that when correlating to acquire, a correlation rate is a factor X=N (bits)×

M (bit rate factor)×

Y (correlators) faster than a correlation rate when tracking the acquired signals.

21. A method according to claim 20 wherein the factor X is chosen to be substantially equal or greater than twice a number of bits in the known code, wherein all possible correlations of the code are performed before the code repeats.

22. An apparatus to process a plurality of received broadcast signals having digital codes, the apparatus comprising:

a sampler unit to sample the received broadcast signals to produce a digital bit stream at a first bit rate in an acquisition mode;

a reducer unit coupled to the sampler unit to reduce a number of bits of the digital bit stream via combination of groups of N bits together to produce a reduced digital bit stream in the acquisition mode; and

a correlator unit coupled to the reducer unit to receive the reduced digital bit stream at a second bit rate and to correlate the reduced digital bit stream with one of the digital codes in the acquisition mode, and wherein the sampler unit is coupled to the correlator unit to directly provide the digital bit stream at the first bit rate to the correlator unit in a track mode and further wherein the correlator unit can correlate that digital bit stream with a different one of the digital codes in the track mode.

23. The apparatus of claim 22 wherein the correlator unit comprises a plurality of correlators to correlate the reduced digital bit stream at the second bit rate with a same one of the digital codes in the acquisition mode.

24. The apparatus of claim 22 wherein the digital codes for the correlations comprise locally generated versions of the digital codes of the received broadcast signals.

25. The apparatus of claim 22 wherein the reducer unit comprises an adder to add the groups of N bits in the acquisition mode to obtain a sum, and wherein further in the acquisition mode:

the adder is coupled to provide a digital output representative of the sum;

the adder is coupled to provide a first binary value if the sum is greater than a given value and a second binary value if the sum is less than the given value; and

the adder is coupled to alternately provide the first binary value and the second binary value if the sum is equal to the given value.

26. The apparatus of claim 22 wherein the second bit rate is higher than the first bit rate in the acquisition mode.

27. The apparatus of claim 22, further comprising a memory arrangement coupled to the correlator unit to receive the reduced digital bit stream and to output the reduced digital bit stream to the correlator unit at the second bit rate.

28. The apparatus of claim 27 wherein the memory arrangement comprises a circulating shift register.

29. A system to process a plurality of received broadcast signals having digital codes, the system comprising:

a means for sampling the received broadcast signals to produce a digital bit stream at a first bit rate;

a means for reducing a number of bits of the digital bit stream by combining groups of N bits to produce a reduced digital bit stream;

a means for correlating the reduced digital bit stream with one of the digital codes to acquire the broadcast signals; and

a means for correlating the digital bit stream at the first bit rate with a different one of the digital codes to track the acquired broadcast signals.

30. The system of claim 29 wherein the means for reducing the number of bits of the digital bit stream includes a means for producing the reduced digital bit stream at a second bit rate higher than the first bit rate.

31. The system of claim 29 wherein the means for reducing the number of bits of the digital bit stream by combining groups of N bits includes a means for summing the groups of N bits to obtain a sum, the means for summing including:

a means for providing a first binary value if the sum is greater than a given value and a second binary value if the sum is less than the given value; and

a means for alternately providing the first binary value and the second binary value if the sum is equal to the given value.