Residual echo reduction for a full duplex transceiver
First Claim
1. A full-duplex transceiver comprising:
- a first signal processing circuit generating an outgoing signal z(t) and a replica signal r2(t), each being proportional to an input signal r0(t), for combining the outgoing signal with an incoming signal y(t) to form a combined signal r1(t) of magnitude proportional to a sum of magnitudes of the outgoing and incoming signals, and for processing the combined signal and the replica signal to produce a received signal p(t) representing the incoming signal, wherein the input signal and the outgoing signal respectively represent first and second sequences of data elements though patterns of periodic transitions between magnitude levels;
a delay circuit supplying the input signal r0(t) to the first signal processing circuit with an adjustable delay controlled by a delay control signal supplied as input to the second delay circuit; and
second signal processing circuit generating both the delay control signal and a soft decision sequence s(n) of data elements in response to the received signal, wherein the soft decision sequence represents the first data sequence also represented by the incoming signal.
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Abstract
A hybrid circuit within a full-duplex transceiver transmits an outgoing signal outward on a communication channel at the same time it receives an incoming signal arriving via the communication channel, and the outgoing and incoming signals sum to form a combined signal. The hybrid circuit generates both the outgoing signal and a replica of the outgoing signal in response to an input signal, and then subtracts the replica from the combined signal in producing a received signal. The received signal includes a component derived from the incoming signal and a residual echo component having peaks resulting from a phase difference between the outgoing signal and its replica. The transceiver periodically digitizes the received signal to produce a data sequence representing the incoming signal. The transceiver adjustably delays the input signal so that the residual echo component peaks occur at times other then when the received signal is being digitized, thereby minimizing the influence of the echo component peaks on the data sequence.
88 Citations
26 Claims
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1. A full-duplex transceiver comprising:
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a first signal processing circuit generating an outgoing signal z(t) and a replica signal r2(t), each being proportional to an input signal r0(t), for combining the outgoing signal with an incoming signal y(t) to form a combined signal r1(t) of magnitude proportional to a sum of magnitudes of the outgoing and incoming signals, and for processing the combined signal and the replica signal to produce a received signal p(t) representing the incoming signal, wherein the input signal and the outgoing signal respectively represent first and second sequences of data elements though patterns of periodic transitions between magnitude levels;
a delay circuit supplying the input signal r0(t) to the first signal processing circuit with an adjustable delay controlled by a delay control signal supplied as input to the second delay circuit; and
second signal processing circuit generating both the delay control signal and a soft decision sequence s(n) of data elements in response to the received signal, wherein the soft decision sequence represents the first data sequence also represented by the incoming signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for positioning residual echo within a received signal p(t) produced by a full-duplex transceiver which generates an outgoing signal z(t) and a replica signal r2(t) in response to an input signal r0(t), each being of magnitude proportional to the input signal, combines the outgoing signal with an incoming signal y(t) to form a combined signal r1(t) of magnitude proportional to a sum of magnitudes of the outgoing and incoming signals, and processes the combined signal and the replica signal to produce the received signal representing the incoming signal, wherein the input signal and the outgoing signal respectively represent first and second sequences of data elements by patterns of periodic transitions between magnitude levels of the input and outgoing signals, wherein the method comprises the steps of:
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a. delaying the input signal r0(t) with an adjustable delay controlled by a delay control signal; and
b. generating both the delay control signal and a soft decision sequence s(n) of data elements in response to the received signal p(t), wherein the soft decision sequence represents the first data sequence also represented by the incoming signal. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A transceiver for transmitting an outgoing signal outward on a communication channel in response to an input signal, at the same time it receives an incoming signal via the communication channel and for generating soft and hard decision sequences of corresponding data elements, each representing a corresponding element of a data sequence represented by the incoming signal, the transceiver comprising:
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a first signal processing circuit for generating both the outgoing signal and a replica of the outgoing signal in response to the input signal, for transmitting the outgoing signal outward via the communication channel, the outgoing and incoming signals forming a combined signal, and for offsetting the combined signal by the replica and processing a resulting signal to produce a received signal including a component derived from the incoming signal and a residual echo component having peaks resulting from a phase difference between the outgoing signal and its replica;
an analog-to-digital converter (ADC) for periodically digitizing the received signal to produce a waveform data sequence;
a second signal processing circuit for processing the waveform data sequence to produce the soft and hard decision data sequences; and
a delay circuit supplying the input signal to the first signal processing circuit with a delay adjusted so that the residual echo component peaks occur in the received signal at times other then when the ADC is digitizing the received signal. - View Dependent Claims (24, 25, 26)
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Specification