Thinning techniques for wafer-to-wafer vertical stacks

• US 20040121556A1
• Filed: 12/19/2002
• Published: 06/24/2004
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kobrinsky, Mauro J., Kim, Sarah E., List, R. Scott
• Granted Patent: US 6,790,748 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include physically removing unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.

Claims

1. A method of fabricating a stacked microelectronic device, comprising:

providing a stacked wafer structure including a first microelectronic wafer attached to a second microelectronic wafer by at least one interconnect layer extending between an active surface of the first microelectronic wafer and an active surface of the second microelectronic wafer, wherein an unsupported portion of said first microelectronic wafer is defined extending between an edge thereof and said at least one interconnect layer; and

physically removing said first microelectronic wafer unsupported portion.

2. The method of claim 1, wherein physically removing said first microelectronic wafer unsupported portion comprises grinding away said first microelectronic wafer portion.

3. The method of claim 1, wherein physically removing said first microelectronic wafer unsupported portion comprises physically removing said first microelectronic wafer portion to form at least one abraded edge having a beveled angle of between about 0 to 60 degrees.

4. The method of claim 1, further comprising thinning said first microelectronic wafer to form a first microelectronic wafer thinned back surface.

5. The method of claim 4, wherein thinning said first microelectronic wafer comprises abrading a back surface of said first microelectronic wafer.

6. The method of claim 5, wherein abrading said first microelectronic wafer back surface is selected from the methods consisting of grinding, spin etching, and chemical mechanical polishing.

7. The method of claim 4, further comprising thinning said first microelectronic wafer to a thickness between about 10 and 100 microns.

8. The method of claim 4, further comprising forming at least one conductive via to extend from said first microelectronic wafer thinned back surface to an integrated circuitry layer proximate said first microelectronic wafer active surface.

9. The method of claim 8, further comprising disposing at least one interconnect device on said at least one conductive via.

10. A method of fabricating a stacked microelectronic device comprising:

providing a first microelectronic wafer having an active surface, a back surface, and at least one edge, said first microelectronic wafer further including an integrated circuitry layer extending from said first microelectronic wafer active surface into said first microelectronic wafer and an interconnect layer on said first microelectronic wafer active surface, wherein a portion of said first microelectronic wafer active surface extending from said at least one first microelectronic wafer edge has not interconnect layer thereon;

providing a second microelectronic wafer having an active surface and an integrated circuitry layer extending from said second microelectronic wafer active surface into said second microelectronic wafer and an interconnect layer on at least a portion of said second microelectronic wafer active surface;

attaching said first microelectronic wafer interconnect layer to said second microelectronic wafer interconnect layer; and

physically removing said first microelectronic wafer portion.

11. The method of claim 10, wherein physically removing said first microelectronic wafer portion comprises grinding away said first microelectronic wafer portion.

12. The method of claim 10, wherein physically removing said first microelectronic wafer portion comprises physically removing said first microelectronic wafer portion to form at least one abraded edge having a beveled angle of between about 0 to 60 degrees.

13. The method of claim 10, wherein physically removing said first microelectronic wafer portion occurs after attaching said first microelectronic wafer interconnect layer to said second microelectronic wafer interconnect layer.

14. The method of claim 10, further comprising thinning said first microelectronic wafer forming a first microelectronic wafer thinned back surface.

15. The method of claim 14, wherein thinning said first microelectronic wafer comprises abrading said first microelectronic wafer back surface.

16. The method of claim 15, wherein abrading said first microelectronic wafer back surface is selected from the methods consisting of grinding, spin etching, and chemical mechanical polishing.

17. The method of claim 14, further comprising thinning said first microelectronic wafer to a thickness between about 10 and 100 microns.

18. The method of claim 13, further comprising forming at least one conductive via to extend from said first microelectronic wafer thinned back surface to said first microelectronic wafer integrated circuitry layer.

19. The method of claim 18, further comprising disposing at least one interconnect device on said at least one conductive via.

20. A method of fabricating a stacked microelectronic device comprising:

providing a first microelectronic wafer having an active surface, a back surface, and at least one edge, said first microelectronic wafer further including an integrated circuitry layer extending from said first microelectronic wafer active surface into said first microelectronic wafer and an interconnect layer on said first microelectronic wafer active surface, wherein a portion of said first microelectronic wafer active surface extending from said at least one first microelectronic wafer edge has not interconnect layer thereon;

providing a second microelectronic wafer having an active surface and an integrated circuitry layer extending from said second microelectronic wafer active surface into said second microelectronic wafer and an interconnect layer on at least a portion of said second microelectronic wafer active surface;

attaching said first microelectronic wafer interconnect layer to said second microelectronic wafer interconnect layer; and

grinding away said first microelectronic wafer portion.

21. The method of claim 20, wherein grinding away said first microelectronic wafer portion comprises grinding said first microelectronic wafer portion to form at least one abraded edge having a beveled angle of between about 0 to 60 degrees.

22. The method of claim 20, further comprising thinning said first microelectronic wafer.