Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same

• US 20040121572A1
• Filed: 12/19/2002
• Published: 06/24/2004
• Est. Priority Date: 07/03/2001
• Status: Active Grant

• Current Assignee: King Owyang, Mohamed N. Darwish
• Original Assignee: King Owyang, Mohamed N. Darwish
• Inventors: Darwish, Mohamed N., Owyang, King
• Granted Patent: US 7,033,876 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place.

Therefore, in embodiments where the thermal budget of the process is limited following the implant of the drain-drift region, the PN junctions between the drain-drift region and the epitaxial layer are self-aligned with the edges of the thick bottom oxide. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The relatively flat dopant profile in the channel region provides an increased punchthrough voltage and low threshold voltage.

Claims

1. A process of fabricating a trench MIS device comprising;

providing a substrate of a first conductivity type;

forming an epitaxial layer on the substrate, the epitaxial layer being being generally of a second conductivity type;

forming a trench in the epitaxial layer;

forming sidewall spacers in the trench;

implanting a dopant of the first conductivity type between the sidewall spacers and through a bottom of the trench;

forming a bottom insulating layer on the bottom of the trench between the sidewall spacers;

removing the sidewall spacers;

forming a gate insulating layer on the sidewalls of the trench, the gate insulating layer being thinner than the bottom insulating layer; and

introducing a conductive material into the trench.

2. The process of claim 1 wherein forming sidewall spacers comprises depositing an insulating layer conformally in the trench and directionally etching the insulating layer so as to remove a portion of the insulating layer at a bottom of the trench, thereby leaving the sidewall spacers adjacent the walls of the trench.

3. The process of claim 2 wherein the insulating layer comprises nitride.

4. The process of claim 1 wherein implanting a dopant of the first conductivity type comprises implanting a dopant at a dose and energy such that following the implant and with substantially no thermal diffusion the dopant extends from the bottom of the trench to the substrate.

5. The process of claim 1 wherein implanting a dopant of the first conductivity type comprises implanting the dopant at a dose and energy such that following the implant the dopant forms a region of the first conductivity type located below the bottom of the trench and not extending to the substrate, the process further comprising heating the epitaxial layer so as to diffuse the dopant downward, thereby forming a drain-drift region extending between the bottom of the trench and the substrate.

6. The process of claim 1 wherein implanting a dopant of the first conductivity type comprises implanting the dopant at a dose and energy such that following the implant the dopant forms a deep layer substantially separated from the trench, the process further comprising heating the epitaxial layer so as to diffuse the dopant upward, thereby forming a drain-drift region extending between the bottom of the trench and the substrate.

7. The process of claim 1 wherein implanting a dopant of the first conductivity type comprises:

implanting a first portion of the dopant at a dose and energy such that following the implant the first portion of dopant forms a region of the first conductivity type located below the bottom of the trench and not extending to the substrate; and

implanting a second portion of the dopant at a dose and energy such that following the implant the second portion of the dopant forms a deep layer substantially separated from the trench;

the process further comprising;

heating the epitaxial layer so as to diffuse the first portion of dopant downward and to diffuse the second portion of dopant upward such that the first and second portions merge, thereby forming a drain-drift region extending between the bottom of the trench and the substrate.

8. The process of claim 1 wherein implanting a dopant of the first conductivity type comprises implanting at least three portions of the dopant at different energies, respectively, so as to form a stack of contiguous regions of the first conductivity type, the stack forming a drain-drift region extending between the bottom of the trench and the substrate.

9. The process of any one of claims 1 through 8 wherein forming a bottom insulating layer comprises depositing a layer and etching the layer to form the bottom insulating layer.

10. The process of claim 9 wherein depositing a layer comprises depositing an oxide layer.

11. The process of claim 10 wherein depositing a layer comprising depositing a layer by chemical vapor deposition.

12. The process of claim 9 wherein the bottom insulating layer is a low-temperature oxide layer.

13. The process of claim 9 wherein depositing a layer comprises depositing a glass layer.

14. The process of any one of claims 1 through 8 wherein forming a bottom insulating layer comprises thermally growing an oxide layer on the bottom of the trench.

15. The process of any one of claims 1 through 8 wherein forming a bottom insulating layer comprises depositing a material that deposits preferentially on the bottom of the trench as compared with the sidewall spacers.

16. A trench MIS device comprising:

a substrate of a first conductivity type;

an epitaxial layer of a second conductivity type on the substrate, a trench being formed in the epitaxial layer;

a gate in the trench;

a gate insulating layer along a sidewall of the trench, the gate being electrically insulated from the epitaxial layer by the gate insulating layer;

a bottom insulating layer on a bottom of the trench, the bottom insulating layer being thicker than the gate insulating layer;

a drain-drift region of the first conductivity type extending between the bottom of the trench and the substrate, the drain-drift region forming a PN junction with the epitaxial layer, the PN junction extending between the trench and the substrate.

17. The trench MIS device of claim 16 wherein the PN junction is concave with respect to the interior of the drain-drift region.

18. The trench MIS device of claim 16 wherein the PN junction extends between the substrate and a side wall of the trench.

19. The trench MIS device of claim 16 wherein the PN junction is aligned with an edge of the bottom insulating layer.

20. A trench MOSFET comprising:

a substrate of a first conductivity type;

an epitaxial layer of a second conductivity type on the substrate, a trench being formed in the epitaxial layer;

a gate in the trench;

a gate insulating layer along a sidewall of the trench, the gate being electrically insulated from the epitaxial layer by the gate insulating layer;

a bottom insulating layer on a bottom of the trench, the bottom insulating layer being thicker than the gate insulating layer;

a drain-drift region of the first conductivity type extending between the bottom of the trench and the substrate, the drain-drift region forming a PN junction with the epitaxial layer, the PN junction extending between the trench and the substrate; and

a source region located adjacent a side wall of the trench and a top surface of the epitaxial layer.

21. The trench MOSFET of claim 20 comprising a threshold adjust implant region of the second conductivity type.

22. The trench MOSFET of claim 21 comprising a body region of the second conductivity type, the body region being doped more heavily than the epitaxial layer.