Flip-chip structure and method for high quality inductors and transformers

• US 20040121606A1
• Filed: 12/23/2002
• Published: 06/24/2004
• Est. Priority Date: 12/23/2002
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Mitchell, Douglas G., Marlin, George W., Raskin, Glenn D.
• Granted Patent: US 6,878,633 B2
• Time in Patent Office: Days
• US Class Current: 438/694
• CPC Class Codes: H01L 2223/6672 for integrated passive components, e.g. semiconductor device with passive components only
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/11472 Profile of the lift-off mask
• CPC Class Codes: H01L 2224/11474 Multilayer masks
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/11902 Multiple masking steps
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A structure and method for achieving a flip-chip semiconductor device having plated copper inductors (4), transformers (16), interconnect, and power busing that is electrically superior, lower cost, and provides for higher quality inductors as well as lower losses for on-chip transformers. Providing a solder dam (8, 24, 28) enables the fabrication of flip-chip solder bumps directly on to inductors and transformers.

Claims

1. ) A process for fabricating a flip-chip structure, comprising the steps of:

depositing a barrier metal seed layer onto a metal bond pad formed on a wafer;

depositing a copper seed layer on said barrier metal seed layer;

electroplating an RF component on said copper seed layer;

depositing a dielectric layer over said RF component;

patterning said dielectric layer to expose a portion of said RF component;

applying a solder mask over said dielectric layer;

patterning a window in said solder mask over said the exposed portion of said RF component;

applying a solder material into said window and down to the exposed portion of said RF component;

reflowing said solder material into a solder bump; and

stripping said solder mask.

2. ) The process of claim 1, wherein said solder material is applied through a squeegee process.

3. ) The process of claim 2, wherein said solder material is a solder paste.

4. ) The process of claim 1, further comprising the step forming sloping side walls on the exposed portion of said dielectric layer.

5. ) The process of claim 4, wherein said sloping side walls are formed through a non-selective etch process.

6. ) The process of claim 1, further comprising the steps of:

depositing a photoresist layer over said copper seed layer;

patterning a component window in said photoresist layer to receive said RF component.

7. ) The process of claim 1, further comprising the step of etching the portions of said copper seed layer and said barrier metal seed layer not under said RF component off said wafer

8. ) A process for forming a flip-chip solder bump on a wafer, comprising the steps of:

depositing a dielectric layer over an RF component formed on said wafer;

forming said dielectric layer into a solder dam through the steps of;

patterning said dielectric layer with a photolithographic process; and

performing a non-selective etch on said dielectric layer to form said solder dam with a sloped wall; and

applying a solder mask over said dielectric layer;

patterning said solder mask to form a window over said solder dam;

applying a solder paste to said wafer through a squeegee process;

reflowing said solder paste into said flip chip solder bump through a thermal process; and

stripping said solder mask.

9. ) The process of claim 8, further comprising the step of inhibiting the flow of said solder paste with said solder dam.

10. ) The process of claim 9, further comprising the step of forming said solder paste into a solder bump with said sloping side walls of said solder dam.

11. ) The process of claim 8, further comprising the step of sealing said wafer with said dielectric layer.

12. ) A flip-chip structure for an RF microchip, comprising;

a wafer;

an RF component formed on said wafer;

a solder dam formed over said RF component leaving a region of said RF component exposed, wherein said solder dam has sloped side walls that surround the exposed region of said RF component; and

a solder bump formed on said RF component within said solder dam.

13. ) The structure of claim 12, further comprising a metal bond pad formed between said wafer and said RF component.

14. ) The structure of claim 13, further comprising:

a titanium/tungsten seed layer formed between said aluminum bond pad and said RF component; and

a copper seed layer formed between said titanium/tungsten seed layer and said RF component.

15. ) The structure of claim 14, further comprising a layer of glass formed over said wafer under said titanium/tungsten seed layer along an outer edge of said RF component.

16. ) A structure to form a flip-chip solder bump structure for RF circuits, comprising;

a wafer;

an RF component formed on said wafer;

solder paste receiving means formed over said RF component to receive an applied solder paste;

solder damming means formed under said solder paste receiving means and over said RF component to form said applied solder paste into a solder bump when said solder paste is melted, wherein said solder damming means is formed over an exposed region of said RF component.

17. ) The structure of claim 16, wherein said solder dam contains the location of said solder paste over the exposed region of said RF component when said solder paste is in a molten state.

18. ) The structure of claim 16, wherein said solder dam is provided with sloping side wall means to shape said solder paste into said solder bump when said solder paste is molten.

19. ) The structure of claim 16, wherein said solder dam means relieves stress placed on said wafer caused by a plastic mold compound deposited over said solder dam means.

20. ) The structure of claim 16, wherein said solder dam forms passivation for said RF component.