Direct conversion receiver

• US 20040121746A1
• Filed: 12/05/2003
• Published: 06/24/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamamoto, Akio, Tanaka, Satoshi, Akamine, Yukinori, Hori, Kazuaki
• Granted Patent: US 7,260,373 B2
• Time in Patent Office: Days
• US Class Current: 455/130
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

In a direct conversion receiver, to cancel a DC offset generated in the baseband processing block, negative feedback arrangements comprising a gain control amplifier and a low-pass filter are respectively attached to the I and Q signal branches of the baseband block following mixer outputs. The gain control amplifier in each negative feedback circuit is gain adjusted so that the product G-B of the gain G of a primary gain control amplifier and its own gain B will be constant and thereby the DC offset is cancelled. This DC offset cancellation can be applied in a continuous receiving system with no intermittent time during a receiving operation. Capacitance elements located off-chip can be reduced to those to be used only in the low-pass filters in the negative feedback circuits, whereas many off-chip capacitance elements have been required to be inserted between each stage of gain control amplifiers in conventional baseband chains.

Claims

1. A direct conversion receiver comprising:

a pair of mixers which convert a receive signal frequency to a baseband frequency; and

a baseband frequency signal processing block including a pair of first amplifiers and a pair of first filters, following said mixers,

wherein said baseband frequency signal processing block further includes a pair of negative feedback circuits with an adjustable feedback factor, each negative feedback circuit including a second filter of low-pass type.

2. The direct conversion receiver according to claim 1,

wherein each said negative feedback circuit comprises a second amplifier and said second filter located, following an output end of the second amplifier.

3. The direct conversion receiver according to claim 2,

wherein said second amplifier is a gain control amplifier.

4. The direct conversion receiver according to claim 2,

wherein said second filter is a low-pass filter with an adjustable cut-off frequency.

5. The direct conversion receiver according to claim 1, further comprising a pair of DC offset cancellation circuits, each comprising:

an analog to digital converter which is connected to an output of one of said pair of first amplifiers to convert analog signals to digital signals;

a digital processing circuit which detects a DC offset voltage out of output signals from said analog to digital converter and calculates a voltage to cancel the DC offset voltage; and

a digital to analog converter which converts a digital signal of the voltage calculated by the digital processing circuit into an analog signal of the voltage and supplies the analog signal of the voltage to said one of said pair of first amplifiers.

6. The direct conversion receiver according to claim 2, further comprising a pair of DC offset cancellation circuits, each comprising:

an analog to digital converter which is connected to an output of one of said pair of first amplifiers to convert analog signals to digital signals;

a digital processing circuit which detects a DC offset voltage out of output signals from said analog to digital converter and calculates a voltage to cancel the DC offset voltage; and

a digital to analog converter which converts a digital signal of the voltage calculated by the digital processing circuit into an analog signal of the voltage and supplies the analog signal of the voltage to said one of said pair of first amplifiers.

7. The direct conversion receiver according to claim 3, further comprising a pair of DC offset cancellation circuits, each comprising:

an analog to digital converter which is connected to an output of one of said pair of first amplifiers to convert analog signals to digital signals;

a digital processing circuit which detects a DC offset voltage out of output signals from said analog to digital converter and calculates a voltage to cancel the DC offset voltage; and

a digital to analog converter which converts a digital signal of the voltage calculated by the digital processing circuit into an analog signal of the voltage and supplies the analog signal of the voltage to said one of said pair of first amplifiers.

8. The direct conversion receiver according to claim 4, further comprising a pair of DC offset cancellation circuits, each comprising:

an analog to digital converter which is connected to an output of one of said pair of first amplifiers to convert analog signals to digital signals;

a digital processing circuit which detects a DC offset voltage out of output signals from said analog to digital converter and calculates a voltage to cancel the DC offset voltage; and

a digital to analog converter which converts a digital signal of the voltage calculated by the digital processing circuit into an analog signal of the voltage and supplies the analog signal of the voltage to said one of said pair of first amplifiers.

9. The direct conversion receiver according to claim 5,

wherein said direct conversion receiver performs DC offset cancellation by means of said pair of DC offset cancellation circuits when being powered on and, subsequently, performs DC offset cancellation by means of said pair of negative feedback circuits.

10. The direct conversion receiver according to claim 6,

wherein said direct conversion receiver performs DC offset cancellation by means of said pair of DC offset cancellation circuits when being powered on and, subsequently, performs DC offset cancellation by means of said pair of negative feedback circuits.

11. The direct conversion receiver according to claim 7,

wherein said direct conversion receiver performs DC offset cancellation by means of said pair of DC offset cancellation circuits when being powered on and, subsequently, performs DC offset cancellation by means of said pair of negative feedback circuits.

12. The direct conversion receiver according to claim 8,

wherein said direct conversion receiver performs DC offset cancellation by means of said pair of DC offset cancellation circuits when being powered on and, subsequently, performs DC offset cancellation by means of said pair of negative feedback circuits.

13. The direct conversion receiver according to claim 1,

wherein said pair of first amplifiers have multistage compositions in which a pair of first-stage amplifiers are a pair of static gain amplifiers to which a pair of DC offset cancellation circuits are attached respectively, each said DC offset cancellation circuit comprising:

an analog to digital converter which is connected to an output of one of said pair of first amplifiers to convert analog signals to digital signals;

a digital processing circuit which detects a DC offset voltage out of output signals from said analog to digital converter and calculates a voltage to cancel the DC offset voltage; and

a digital to analog converter which converts a digital signal of the voltage calculated by the digital processing circuit into an analog signal of the voltage and supplies the analog signal of the voltage to said one of said pair of first amplifiers.

14. The direct conversion receiver according to claim 13,

wherein said pair of static gain amplifiers perform DC offset cancellation by means of said pair of DC offset cancellation circuits when said direct conversion receiver is powered on and, subsequently, DC offset cancellation is performed by means of said pair of negative feedback circuits.

15. The direct conversion receiver according to claim 1,

wherein each of said pair of first amplifiers is made up of multiple stages of gain control amplifiers and a last-stage static gain amplifier and each said negative feedback circuit loops back to an output of a first-stage gain control amplifier.

16. The direct conversion receiver according to claim 2,

wherein each of said pair of first amplifiers is made up of multiple stages of gain control amplifiers and a last-stage static gain amplifier and each said negative feedback circuit loops back to an output of a first-stage gain control amplifier.

17. The direct conversion receiver according to claim 3,

wherein each of said pair of first amplifiers is made up of multiple stages of gain control amplifiers and a last-stage static gain amplifier and each said negative feedback circuit loops back to an output of a first-stage gain control amplifier.

18. The direct conversion receiver according to claim 1,

wherein said pair of first amplifiers are pair of gain control amplifiers having circuitry in which a plurality of different resistance elements are located so as to connect to a common terminal of the emitter side of a couple of differential transistors and gain is changed in steps by switching on/off current flowing through the plurality of resistance elements.

19. The direct conversion receiver according to claim 2,

wherein said pair of first amplifiers are pair of gain control amplifiers having circuitry in which a plurality of different resistance elements are located so as to connect to a common terminal of the emitter side of a couple of differential transistors and gain is changed in steps by switching on/off current flowing through the plurality of resistance elements.

20. The direct conversion receiver according to claim 3,

wherein said pair of first amplifiers are pair of gain control amplifiers having circuitry in which a plurality of different resistance elements are located so as to connect to a common terminal of the emitter side of a couple of differential transistors and gain is changed in steps by switching on/off current flowing through the plurality of resistance elements.