System for controlling data transfer protocol with a host bus interface

• US 20040122988A1
• Filed: 04/18/2003
• Published: 06/24/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Choi, Yong Seok, Kim, Myung-Joon, Moh, Sang Man, Han, Jong Seok, Rim, Kee-Wook
• Granted Patent: US 6,871,237 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.

Claims

1. A data transfer protocol control system with a host bus interface, the system comprising:

a transmitting/receiving command DMA including a command DMA request buffer and a command DMA response buffer to interface data transfer protocol control device, for instructing the command DMA request buffer to read command message data and providing the command DMA request buffer with address information of a corresponding host memory when reading the command message data, and for instructing the command DMA request buffer to write and providing the command DMA request buffer with the address information of the corresponding host memory and the command message data when writing the command message data;

a transmitting data DMA including a transmitting data DMA request buffer, a transmitting data DMA response buffer and a transmitting data buffer to interface data transfer protocol control device, for instructing the transmitting data DMA request buffer to read the command message data and providing the transmitting data DMA request buffer with address information of a corresponding host memory and storing position address information of the transmitting data buffer;

a receiving data DMA including a receiving data DMA request buffer, a receiving data DMA response buffer and a receiving data buffer to interface data transfer protocol control device, for instructing the receiving data DMA request buffer to write the command message data and providing the receiving data DMA request buffer with address information of a corresponding host memory and storing position address information of the receiving data buffer; and

a data transfer protocol control device for putting read information on a host bus, receiving the command message data from the host memory and a transfer response signal representing whether reading is completed or not, and storing the transfer response signal in the command DMA response buffer when the command message data in the command DMA request buffer is a reading command, for putting write information and the command message data on the host bus, receiving the transfer response signal representing whether writing is completed or not, and storing the transfer response signal in the command DMA response buffer when the command message data in the command DMA request buffer is a writing command, for ascertaining a command of the transmitting data DMA request buffer, putting the ascertained command on the host bus, sorting data messages from the host memory at the position indicated by a storing address of the transmitting data buffer, receiving a transfer response signal representing whether reading is completed or not, and storing the transfer response signal in the transmitting data DMA response buffer, and for ascertaining a command of the receiving data DMA request buffer, putting the ascertained command and the data messages stored in the receiving data DMA request buffer on the host bus, receiving a transfer response signal representing whether writing is completed or not, and storing the transfer response signal in the receiving data DMA response buffer.

2. The system as claimed in claim 1, wherein the command DMA request buffer accommodates eight packets wherein each of request packet includes a request packet header and a host memory address section when requesting to read, and each of request packet includes a request packet header, a host memory address section and a write message data section when requesting to write;

and

the command DMA response buffer accommodates eight packets wherein each of response packet includes a response packet header, a host memory address section and a read message data section when responding to read, and each of response packet includes a response packet header and a host memory address section when responding to write.

3. The system as claimed in claim 2, wherein the request packet header includes a command field, a byte enable field, a DMA ID field, a transaction ID field and a message size field;

and

the host memory address section is expressed in 64 bits and divided into two fields of 32 bits to store host memory address data.

4. The system as claimed in claim 2, wherein the response packet header further has a 2-bit state field to store a transfer response signal representing whether normal transfer is completed or not compared with the request packet header.

5. The system as claimed in claim 1, wherein the transmitting data DMA response buffer accommodates 16 packets each of which includes a request packet header and a host memory address section;

and

the transmitting data DMA response buffer accommodates 16 packets each of which includes only a response packet header.

6. The system as claimed in claim 1, wherein request packet headers of the transmitting data DMA request buffer and the receiving data DMA request buffer include a command field, a byte enable field, a transmitting data buffer address field, a packet interconnection field, a DMA ID field, a transaction ID field, a subtransaction ID field and a message size field.

7. The system as claimed in claim 6, wherein the transmitting data DMA and the receiving data DMA request a data message from the host memory by:

setting the packet interconnection field to be ‘

00’

when requesting one complete message;

setting the packet interconnection field to be ‘

01’

when dividing a message and requesting a first divided message;

setting the packet interconnection field to be ‘

10’

when dividing a message and requesting a middle divided message;

setting the packet interconnection field to be ‘

11’

when dividing a message and requesting a last divided message.

8. The system as claimed in claim 6, wherein the transmitting data DMA and the receiving data DMA set the DMA ID field and the transaction ID field of the request packet headers thereof to be distinguishable DMA ID value and transaction ID value that indicate packet of the transmitting data DMA request buffer respectively, and use the subtransaction ID field when further dividing a message and requesting the further divided message.

9. The system as claimed in claim 6, wherein the data transfer protocol control device transmits the read information to the host bus and analyzes a transfer response signal from the host bus when performing a read command of the transmitting/receiving command DMA;

the data transfer protocol control device sets a transfer complete bit of the state field of the response packet header of the command DMA response buffer when the transfer response signal indicates normal transfer;

the data transfer protocol control device sets a transfer error bit of the state field of the response packet header of the command DMA response buffer when the transfer response signal indicates transfer error; and

the data transfer protocol control device stores metadata of request packet of a current state in an internal table when the transfer response signal indicates separate response, and finishes final transfer when a response message arrives.

10. The system as claimed in claim 1, wherein the data transfer protocol control device transmits the read information to the host bus and analyzes a transfer response signal from the host bus when performing a read command of the transmitting/receiving command DMA;

the data transfer protocol control device sets a transfer complete bit of the state field of the response packet header of the command DMA response buffer when the transfer response signal indicates normal transfer; and

the data transfer protocol control device sets a transfer error bit of the state field of the response packet header of the command DMA response buffer when the transfer response signal indicates transfer error.

11. The system as claimed in claim 1, wherein the data transfer protocol control device transmits the read information to the host bus and analyzes a transfer response signal from the host bus when performing a read command of the transmitting data DMA;

the data transfer protocol control device ascertain whether either a single message or a last message is transferred or either a first message or a middle successive message is transferred when the transfer response signal indicates normal transfer;

the data transfer protocol control device stores received message data in the transmitting data buffer, closes the transmitting data buffer and sets a transfer complete bit of the response packet header of the command DMA response buffer when the single message or the last message is transferred;

the data transfer protocol control device stores received message data in the transmitting data buffer, does not close the transmitting data buffer and sets a transfer complete bit of the response packet header of the command DMA response buffer when the first message or the middle message is transferred;

the data transfer protocol control device sets a transfer error bit of the state field of the response packet header of the command DMA response buffer when the transfer response signal indicates transfer error; and

the data transfer protocol control device stores metadata of request packet of a current state in an internal table when the transfer response signal indicates separate response, and finishes final transfer when a response message arrives.

12. The system as claimed in claim 1, wherein the data transfer protocol control device transmits the write information to the host bus and analyzes a transfer response signal from the host bus when performing a write command of the receiving data DMA;

the data transfer protocol control device ascertain whether either a single message or a last message is transferred or either a first message or a middle successive message is transferred when the transfer response signal indicates normal transfer;

the data transfer protocol control device clears the receiving data buffer and sets a transfer complete bit of the response packet header of the command DMA response buffer when the single message or the last message is transferred;

the data transfer protocol control device does not clear the receiving data buffer and sets a transfer complete bit of the response packet header of the command DMA response buffer when the first message or the middle message is transferred; and

the data transfer protocol control device sets a transfer error bit of the state field of the response packet header of the command DMA response buffer when the transfer response signal indicates transfer error.