Method and apparatus for detecting an error in a bit sequence
First Claim
1. A bit error detection circuit comprising:
- a predictor circuit that uses a plurality of bits of a bit sequence to predict a next bit in the sequence;
a comparator circuit that compares an actual next bit in the sequence with the predicted next bit to determine whether there is any error in the actual next bit; and
a correction circuit that corrects any error in the actual next bit to provide a corrected actual next bit.
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Accused Products
Abstract
An error detector for a pseudo-random bit sequence (PRBS). A plurality of bits of a PRBS are received in a predictor circuit. A comparator compares two of the bits to predict a next bit in the sequence. The predicted next bit is compared with the actual next bit that is received to determine if there is an error in the actual next bit, and if so, the actual next bit is corrected accordingly. The erroneous actual next bit is replaced with the corrected actual next bit and is then used to predict a future actual next bit. A trigger circuit delays correction during initial operation until the predictor contains a bit sequence in which no errors have been detected.
24 Citations
22 Claims
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1. A bit error detection circuit comprising:
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a predictor circuit that uses a plurality of bits of a bit sequence to predict a next bit in the sequence;
a comparator circuit that compares an actual next bit in the sequence with the predicted next bit to determine whether there is any error in the actual next bit; and
a correction circuit that corrects any error in the actual next bit to provide a corrected actual next bit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A bit error detection circuit comprising:
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a shift register that receives N bits of a pseudo-random bit sequence (PRBS);
a first logic element that receives output signals from two stages of the shift register and provides a signal indicative of a predicted (N+1)-th bit;
a second logic element that receives the signal indicative of the predicted (N+1)-th bit and a signal indicative of an actual (N+1)-th bit and provides an output signal indicative of any error in the actual (N+1)-th bit; and
a third logic element that receives the output signal and corrects the actual (N+1)-th bit according to the output signal as the (N+1)-th bit propagates through the shift register. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of detecting errors in a bit sequence comprising:
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predicting a next bit of a bit sequence according to a plurality of previous bits of the sequence;
comparing the predicted bit with an actual next bit; and
if the comparison indicates a difference between the predicted and actual next bits, providing an error signal and correcting the actual next bit. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A bit error detector comprising:
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an actual next bit input that receives a plurality of bits of a bit sequence;
a predictor coupled to the input and having a predicted next bit output;
a comparator coupled to the predicted next bit output and to the actual next bit input, the comparator having an error signal output; and
a corrector coupled to the error signal output and having a corrected actual next bit output. - View Dependent Claims (22)
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Specification