Low-capacitance electrostatic discharge protection diodes

• US 20040124473A1
• Filed: 12/31/2002
• Published: 07/01/2004
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Poon, Steven S., Maloney, Timothy J.
• Granted Patent: US 7,847,317 B2
• Time in Patent Office: Days
• US Class Current: 257/360
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0814 Diodes only

Abstract

A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Claims

1. An apparatus comprising:

a first conductive layer to provide conductive interconnects for pad and supply diffusion regions in a diode;

a second conductive layer including a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply,

lines of the first and second conductive layers being substantially parallel to each other in a diode region of the diode.

2. The apparatus of claim 1 wherein

a width of at least one supply diffusion region is substantially larger than a minimum width associated with the supply diffusion region for a process on which the diode is manufactured.

3. The apparatus of claim 2 wherein

a width of the at least one supply diffusion region is at least 50% larger than a minimum width associated with the supply diffusion region for the process on which the diode is manufactured.

4. The apparatus of claim 2 wherein

the first portion of the second metal layer to couple the pad regions to a pad extends less than half way across the diode region from a first side of the diode region, and wherein

the second portion of the second metal layer to couple the supply regions to a voltage supply extends less than half way across the diode region from an opposite side of the diode region.

5. The apparatus of claim 2 wherein

each of the first and second portions of the second metal layer includes lines that extend across substantially the entire diode region.

6. A diode comprising:

at least a first supply diffusion region having a width that is substantially larger than a minimum width for the first supply region;

a first metal layer to provide interconnects for pad and supply diffusion regions including the at least first supply diffusion region; and

a second metal layer including a first portion to couple the pad diffusion regions to a pad and a second portion to coupled the supply diffusion regions to receive a supply voltage, lines of the first and second metal layers being substantially parallel to each other in a diode region of the diode.

7. The diode of claim 6 wherein

the at least first supply diffusion region has a width at least 50% larger than the minimum width.

8. The diode of claim 7 wherein

the pad diffusion regions have a width substantially equal to a minimum width for the pad diffusion regions associated with a process on which the diode is fabricated.

9. The diode of claim 6 wherein

lines associated with each of the first and second portions of the second metal layer extend across less than 50% of the diode region from opposite sides of the diode region.

10. The diode of claim 6 wherein

lines associated with each of the first and second portions of the second metal layer extend across substantially an entire width of the diode region and the width of the supply diffusion region is at least 100% larger than a minimum width for the supply diffusion region.

11. An input buffer comprising:

a pad to receive an input signal;

a first diode having a first terminal coupled to the pad and a second terminal coupled to receive a first supply voltage; and

a second diode having a first terminal coupled to the pad and a second terminal coupled to receive a second supply voltage,

wherein, at least one of the first and second diodes includes a lower level metal layer and an adjacent higher level metal layer, lines of the lower level metal layer and higher level metal layer being substantially parallel to each other in a diode region of the at least one diode.

12. The input buffer of claim 11 wherein the at least one diode further comprises:

pad diffusion regions coupled to the pad and supply diffusion regions coupled to receive the respective supply voltage, wherein the supply diffusion regions are substantially wider than a minimum width for the supply diffusion regions and the pad diffusion regions are substantially at a minimum width for the pad diffusion regions.

13. The input buffer of claim 12 wherein

the supply diffusion regions for the at least one diode are at least 50% wider than a minimum width for the supply diffusion regions.

14. The input buffer of claim 12 wherein

the higher level metal layer of the at least one diode includes a first portion to couple the pad diffusion regions to the pad and a second portion to couple the supply diffusion regions to receive the respective supply voltage, metal lines of the first and second portions extending less than 50% across the diode region from opposite sides of the diode region.

15. The input buffer of claim 12 wherein

the higher level metal layer of the at least one diode includes a first portion to couple the pad diffusion regions to the pad and a second portion to coupled the supply diffusion regions to receive the respective supply voltage, metal lines of the first and second portions extending across substantially an entire width of diode region from opposite sides of the diode region.

16. A method comprising:

providing tap diffusion regions in a diode that are substantially wider than a minimum width for the tap diffusion regions;

providing pad diffusion regions;

providing a first conductive layer having lines that extend in a first direction across a diode region of the diode, the first conductive layer having conductive lines that are coupled to the pad and tap diffusion regions; and

providing a second adjacent conductive layer having lines that are substantially parallel to the lines of the first conductive layer in the diode region.

17. The method of claim 16 wherein

providing the tap diffusion regions includes providing tap diffusion regions that are at least 50% wider than a minimum width for the tap diffusion regions.

18. The method of claim 16 wherein

providing the second conductive layer includes

providing a first portion of the second conductive layer including first lines to couple the pad diffusion regions to a pad, and

providing a second portion of the second conductive layer including second lines to couple the tap diffusion regions to receive a supply voltage,

each of the first and second lines extending less than 50% across the diode region from opposite sides of the diode region.

19. The method of claim 16 wherein

providing the second conductive layer includes

providing a first portion of the second conductive layer including first lines to couple the pad diffusion regions to a pad, and

providing a second portion of the second conductive layer including second lines to couple the tap diffusion regions to receive a supply voltage,

each of the first and second lines extending substantially across the entire diode region from opposite sides of the diode region.

20. The method of claim 19 wherein

providing the tap diffusion regions includes providing tap diffusion regions that are at least 100% wider than a minimum width for the tap diffusion regions.