Gap tuning for surface micromachined structures in an epitaxial reactor

• US 20040124483A1
• Filed: 12/31/2002
• Published: 07/01/2004
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Partridge, Aaron, Lutz, Markus
• Granted Patent: US 6,808,953 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 3/0086 Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage
• CPC Class Codes: B81C 1/00063 Trenches
• CPC Class Codes: B81C 2201/0112 Bosch process
• CPC Class Codes: B81C 2203/0136 Growing or depositing of a covering layer
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid

Abstract

A method for adjusting with high precision the width of gaps between micromachined structures or devices in an epitaxial reactor environment. Providing a partially formed micromechanical device, comprising a substrate layer, a sacrificial layer including silicon dioxide deposited or grown on the substrate and etched to create desired holes and/or trenches through to the substrate layer, and a function layer deposited on the sacrificial layer and the exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Cleaning residues from the surface of the device, then epitaxially depositing a layer of gap narrowing material selectively on the surfaces of the device. The selection of deposition surfaces determined by choice of materials and the temperature and pressure of the epitaxy carrier gas. The gap narrowing epitaxial deposition continues until a desired gap width is achieved, as determined by, for example, an optical detection arrangement. Following the gap narrowing step, the micromachined structures or devices may be released from their respective underlying sacrificial layer.

Claims

1. A method for tuning a gap between a plurality of faces of at least one micromechanical element on a device, comprising:

etching an outline of the at least one micromechanical element in a top layer of the device, the outline defining at least two opposing faces of the plurality of faces of the at least one micromechanical element; and

depositing in an epitaxial reactor a gap-narrowing layer on the at least two opposing faces of the plurality of faces;

wherein a gap between the at least two opposing faces of the plurality of faces is narrowed by the gap-narrowing layer.

2. The method of claim 1, wherein the gap-narrowing layer includes a silicon layer.

3. The method of claim 1, wherein the gap-narrowing layer includes a germanium layer.

4. The method of claim 1, wherein the gap-narrowing layer includes a silicon/germanium layer.

5. The method of claim 1, wherein the device includes:

a substrate layer;

a sacrificial layer deposited on at least a first portion of the substrate layer; and

a function layer deposited on at least a second portion of the sacrificial layer to form the top layer.

6. The method of claim 5, wherein:

the sacrificial layer includes silicon dioxide; and

during the deposition of the gap narrowing layer, deposition on the sacrificial layer is selectively avoided by adjusting at least one of a temperature, a pressure, and a gas composition of the epitaxial reactor.

7. The method of claim 6, wherein the gas composition of the epitaxial reactor includes a compound of at least one of bromine, chlorine, fluorine and hydrogen.

8. The method as recited in claim 5, further comprising at least one of

providing a further sacrificial layer;

and

providing a further function layer.

9. The method as recited in claim 8, wherein the at least one of the providing of the further sacrificial layer and the providing of the further function layer is performed before the etching of the outline operation.

10. The method as recited in claim 8, further comprising etching the further sacrificial layer.

11. The method of claim 1, wherein the device includes an SOI wafer, an insulator layer of the SOI wafer forming a sacrificial layer and a top silicon layer of the SOI wafer forming the top layer.

12. The method of claim 1, wherein the depositing operation further comprises:

entraining one of silane, dichlorosilane and trichlorosilane in an H₂ flow; and

passing the H₂ flow over the device.

13. The method of claim 1, further comprising:

detecting a remaining gap width, and

terminating the deposition of the gap narrowing layer when the remaining gap width is about equal to a desired gap width.

14. The method of claim 13, wherein the detecting operation includes detecting the remaining gap width with an optical detector.

15. The method of claim 14, wherein the optical detector detects an interference pattern from light refracted from the device.

16. The method of claim 14, wherein:

the optical detector detects a first light reflection reflected from an upper surface of the device and a second light reflection reflected from a lower surface of the device;

the first light reflection includes at least one of a first light intensity and a first light phase;

the second light reflection includes at least one of a second light intensity and a second light phase; and

a ratio between the first light reflection and the second light reflection is determined.

17. The method of claim 1, wherein the deposition of the gap narrowing layer includes a selective deposition process.

18. The method of claim 1, wherein the deposition of the gap narrowing layer includes a conformal deposition process.

19. A device comprising:

a top layer having at least two opposing faces; and

at least two epitaxially deposited layers, each of the at least two epitaxially deposited layers situated on a respective one of the at least two opposing faces, a combined thickness of the at least two epitaxially deposited layers tuning a gap between the at least two opposing faces.

20. The device of claim 19, wherein at least one of the at least two epitaxially deposited layers includes at least one of a silicon layer, a germanium layer and a silicon/germanium layer.

21. The device of claim 19, wherein the at least two opposing faces define at least one micromechanical element in the top layer of the device.

22. The device of claim 19, further comprising:

a substrate layer; and

a sacrificial layer deposited on a first portion of the substrate layer;

wherein the top layer includes at least one function layer epitaxially deposited on at least a second portion of the the sacrificial layer.

23. The device as recited in claim 22, further comprising:

a further sacrificial layer arranged below the substrate layer;

wherein the further sacrificial layer is released from the substrate layer by exposing the device to gaseous hydrogen.

24. The device of claim 22, wherein:

the sacrificial layer includes silicon dioxide; and

during the deposition of the gap narrowing layer, deposition on the sacrificial layer is selectively avoided by adjusting at least one of a temperature, a pressure, and a gas composition of the epitaxial reactor.

25. The device of claim 19, further comprising an SOI wafer, an insulator layer forming a sacrificial layer and a top silicon layer forming the top layer.

26. The device of claim 19, wherein at least one of the at least two epitaxially deposited layers is deposited in an environment including one of silane, dichlorosilane, and trichlorosilane, the one of silane, dichlorosilane, and trichlorosilane entrained in an H₂ flow.

27. The device of claim 19, wherein the at least two epitaxially deposited layers are deposited in an epitaxy reactor environment.

28. The device of claim 19, wherein the gap between the at least two opposing faces defines a desired gap width for at least one micromechanical element arranged on the device.

29. The device of claim 19, wherein the at least two epitaxially deposited layers are deposited in a single process operation.