Method for forming a printed circuit board and a printed circuit board formed thereby

• US 20040124493A1
• Filed: 10/20/2003
• Published: 07/01/2004
• Est. Priority Date: 04/19/2001
• Status: Active Grant

• Current Assignee: GUL Technologies Singapore Limited (Greenwich Pacific Pte Ltd.)
• Original Assignee: GUL Technologies Singapore Limited (Greenwich Pacific Pte Ltd.)
• Inventors: Chua, Ah Lim
• Granted Patent: US 7,019,959 B2
• Time in Patent Office: Days
• US Class Current: 257/508
• CPC Class Codes: H05K 1/0263 High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board H05K1/0293 takes precedence
• CPC Class Codes: H05K 1/0265 characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/09672 Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236
• CPC Class Codes: H05K 2201/09736 Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
• CPC Class Codes: H05K 2203/0369 Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
• CPC Class Codes: H05K 3/243 characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/4611 by laminating two or more circuit boards H05K3/4652 takes precedence

Abstract

Upper, inner and lower sections (182, 180 and 184) of a PCB (100) are formed with each section having a substrate (140, 150 and 160) having patterned layers of metallization (105 and 110, 115 and 120, and 125 and 130), respectively Some of the patterned layers of metallization (110, 115, 120, and 125) have thicker portions(171, 173) and part (188) of portion(186), and thinner portions(172, 174, 187, 190, 191, 192 and 193). The resultant thinner portion(175 and 194)in the prepreg layers (145 and 155) with the respective thicker portions of metallization provide decoupling capacitors, while the resultant thicker portions (196 and 198), for example, provide a lower capacitance for improved trace impedance for the signal traces (191 and 192).

Claims

1. A multi-layered substrate comprising:

a substantially homogenous dielectric layer having a substantially uniform dielectric constant, the dielectric layer having a first surface and a second surface, and the dielectric layer having thicker portions and thinner portions between the first and second surfaces;

a first conductive layer on the first surface of the dielectric layer; and

a second layer comprising a plurality of conductive pieces on the second surface of the dielectric layer,

wherein a first of the plurality of conductive pieces, one of the thicker portions of the dielectric layer, and the first conductive layer form a first capacitor, and

wherein a second of the plurality of conductive pieces, one of the thinner portions of the dielectric layer, and the first conductive layer form a second capacitor.

2. A multi-layered substrate in accordance with claim 1 wherein the first conductive layer comprises a plurality of conductive pieces,

wherein the first of the plurality of conductive pieces of the second layer, the one of the thicker portions of the dielectric layer, and a first of the plurality of conductive pieces of the first conductive layer form the first capacitor, and

wherein the second of the plurality of conductive pieces of the second layer, the one of the thinner portions of the dielectric layer, and a second of the plurality of conductive pieces of the first conductive layer form the second capacitor.

3. A multi-layered substrate in accordance with claim 2 wherein the first of the plurality of conductive pieces of the second layer, the one of the thicker portions of the dielectric layer, and the first of the plurality of conductive pieces of the first conductive layer are substantially aligned along a first common axis extending between the first conductive layer and the second layer.

4. A multi-layered substrate in accordance with claim 2 wherein the second of the plurality of conductive pieces of the second layer, the one of the thinner portions of the dielectric layer, and the second of the plurality of conductive pieces of the first conductive layer are substantially aligned along a second common axis extending between the first conductive layer and the second layer.

5. A multi-layered substrate in accordance with claim 2 wherein the first and second of the plurality of conductive pieces of the first conductive layer have substantially unequal thickness extending from a first common plane.

6. A multi-layered substrate in accordance with claim 2 wherein the first and second of the plurality of conductive pieces of the first conductive layer have substantially equal thickness extending from a first common plane.

7. A multi-layered substrate in accordance with claim 2 wherein the first and second of the plurality of conductive pieces of the second layer have substantially equal thickness extending from a common plane.

8. A multi-layered substrate in accordance with claim 2 wherein the first and second of the plurality of conductive pieces of the second layer have substantially unequal thickness extending from a common plane.

9. A printed circuit board comprising:

at least one substantially homogenous dielectric layer having at least a first portion with a first thickness and having at least a second portion with a second thickness, wherein the second thickness is different from the first thickness;

at least a first pair of metallization layers having the at least the first portion therebetween forming a first capacitor with a first value.

at least a second pair of metallization layers having the at least the second portion therebetween forming a second capacitor with a second value different from the first value.

10. A multi-layered substrate in accordance with claim 9 wherein the at least one dielectric layer comprises a contoured dielectric layer having a range of thickness including the first thickness and the second thickness to provide a range of capacitor values.

11. A multi-layered substrate in accordance with claim 9, wherein at least one of each of the first and second pairs of metallization layers are substantially aligned with a horizontal plane.

12. A substrate comprising:

a substantially homogenous layer of dielectric material having a first surface and a second surface, wherein the second surface is opposite the first surface; and

a plurality of conductive portions comprising;

at least a first pair of the plurality of conductive portions,

wherein one of the first pair of the plurality of conductive portions being disposed in the layer of dielectric material proximal to the first surface, wherein at least part of the one of the first pair of the plurality of conductive portions extending from the first surface towards the second surface, and

wherein the other one of the first pair of the plurality of conductive portions being disposed proximal to the second surface and being spaced apart from the at least part of the one of the first pair of the plurality of conductive portions by a first distance; and

at least a second pair of the plurality of conductive portions,

wherein one of the second pair of the plurality of conductive portions being disposed in the layer of dielectric material proximal to the first surface, wherein at least part of the one of the second pair of the plurality of conductive portions extending from the first surface towards the second surface, and

wherein the other one of the second pair of conductive portions being disposed proximal to the second surface and being spaced apart from the at least part of the one of the second pair of conductive portions by a second distance, wherein the first distance is greater than the second distance.

13. A method for forming a multi-layered substrate comprising:

a) forming a plurality of sections, each of the plurality of sections comprising at least one substrate layer and at least one patterned layer of metallization, wherein the patterned layer of metallization has thicker portions and thinner portions;

b) stacking the plurality of sections with intervening layers of dielectric material;

c) forming the stack of the plurality of sections and the intervening layers of dielectric material into the multi-layered substrate.

14. A method in accordance with claim 13, wherein step (a) comprises the steps of:

d) providing a substrate;

e) forming a first patterned layer of metallization on at least one surface of the substrate;

f) forming a second patterned layer of metallization on the first patterned layer of metallization.

15. A method in accordance with claim 14, wherein step (e) comprises the steps of:

forming a first mask on the at least one surface of the substrate;

depositing metal on the masked at least one surface; and

stripping the first mask.

16. A method in accordance with claim 14, wherein step (f )comprises the steps of:

forming a second mask on the first patterned layer of metallization on at least one surface of the substrate; and

depositing metal on the masked first patterned layer of metallization on the at least one surface of the substrate

stripping the second mask.

17. A method in accordance with claim 13, wherein step (a) comprises the steps of:

g) providing a laminate having a substrate layer and a layer of metallization;

h) etching the layer of metallization in accordance with the first predetermined pattern to produce an etched laminate; and

i) etching the etched laminate in accordance with the second predetermined pattern of metallization.

18. A method in accordance with claim 17, wherein step (h) comprises the steps of:

forming a first mask on the on the layer of metallization;

exposing the masked layer of metallization to an etchant that removes exposed portion of the layer of metallization; and

stripping the first mask.

19. A method in accordance with claim 17, wherein step (i) comprises the steps of:

forming a second mask on the etched laminate;

exposing the masked etched laminate to an etchant that removes exposed portion of the layer of metallization; and

stripping the second mask.

20. A method in accordance with claim 13, wherein step (a) comprises the steps of:

j) providing a laminate having a substrate layer and a layer of metallization;

k) etching the layer of metallization in accordance with a first predetermined pattern to produce an etched laminate; and

l) forming a layer of metallization on the etched laminate in accordance with a second predetermined pattern.

21. A method in accordance with claim 20, wherein step (k) comprises the steps of:

forming a first mask on the layer of metallization in accordance with the first predetermined pattern;

exposing the masked layer of metallization to an etchant that removes exposed portions of the layer of metallization; and

stripping the first mask.

22. A method in accordance with claim 20, wherein step (1) comprises the steps of:

forming a second mask on the etched layer of metallization in accordance with the second predetermined pattern;

depositing metal on exposed portions of the etched layer of metallization; and

stripping the second mask.

23. A method in accordance with claim 13, prior to step (b) comprises the step of providing the layers of dielectric material.

24. A method in accordance with claim 23, wherein the step of providing the layers of dielectric material comprises the step of providing pre-cut layers of prepreg.

25. A method in accordance with claim 23, prior to the step of providing the layers of dielectric material comprises the step of forming the layers of dielectric material.

26. A method in accordance with claim 25, wherein the step of forming the layers of dielectric comprises the step of molding the layers of dielectric material.

27. A method in accordance with claim 13, wherein step (c) comprises the step of aligning the at least one patterned layer of metallization in each of the plurality of sections and the intervening layers of dielectric material.

28. A method in accordance with claim 27, wherein step (c) further comprises the step of disposing adhesive between the plurality of sections and the intervening layers of dielectric material.

29. A method in accordance with claim 27, wherein step (c) further comprises the step of applying pressure to compress the at least one patterned layer of metallization in each of the plurality of sections and the intervening layers dielectric material.

30. A method in accordance with claim 29, wherein step (c) further comprises the step of applying heat.