Method and apparatus for supplying power to a semiconductor device using a capacitor DC shunt

• US 20040124511A1
• Filed: 12/31/2002
• Published: 07/01/2004
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Li, Yuan-Liang
• Granted Patent: US 7,317,622 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H05K 1/0206 by printed thermal vias
• CPC Class Codes: H05K 1/0212 Printed circuits or mounted components having integral heating means
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/145 Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
• CPC Class Codes: H05K 2201/09481 Via in pad; Pad over filled via if used for surface mounting H05K1/113
• CPC Class Codes: H05K 2201/10325 Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support
• CPC Class Codes: H05K 2201/10515 Stacked components
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/3494 Heating methods for reflowing of solder using integral heating means H05K1/0212

Abstract

A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.

Claims

1. A semiconductor device comprising:

a motherboard having first and second type conductive portions embedded therein coupled to a power source;

a socket portion defined on and projecting above an upper surface of the motherboard and electrically coupled to the first and second type conductive portions;

a package coupled to the motherboard via the socket portion, said package having a suspended portion between the sockets wherein an underside of the suspended portion is spaced from an opposing upper surface portion of the motherboard;

package conductors within the package adapted to transmit current from a bottom surface to a top surface of the package;

a die load affixed to a top surface of the package above the suspended portion and electrically coupled via the package conductors through the socket portion to the first and second type conductive portions to provide a first power source path for the die load; and

a capacitor located within the space between the suspended portion of the package and the opposing upper surface portion of the motherboard, said capacitor being electrically coupled between the first and second type conductive portions within the motherboard and the package conductors to provide a second power source path for the die load.

2. The semiconductor device of claim 1, said capacitor including:

a conductive layer of a first type;

a conductive layer of a second type;

a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer; and

terminals of a first type and a second type located along a first side of the capacitor and along an opposing side of the capacitor, said terminals coupled to respective type conductive layers of the capacitor, said first side terminals electrically coupled to respective first and second type conductive portions within the motherboard and said opposing side terminals electrically coupled to said package conductors.

3. The semiconductor device of claim 2, said first and second type conductive layers and dielectric layer disposed oblique relative to the upper surface of the motherboard.

4. The semiconductor device of claim 2, wherein said capacitor includes a plurality of conductive layers of a first type and a plurality of conductive layers of a second type electrically isolated from the layers of the first type by a plurality of dielectric layers.

5. The semiconductor device of claim 1, said capacitor including:

a conductive layer of a first type;

a conductive layer of a second type;

a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer; and

terminals of a first type and a second type located along a first side of the capacitor and along an opposing side of the capacitor, said terminals coupled between the motherboard and the package and electrically coupling the first and second type conductive portions within the motherboard and the package conductors to respective type conductive layers of the capacitor.

6. The semiconductor device of claim 5, said first and second type conductive layers and dielectric layer disposed parallel relative to the upper surface of the motherboard.

7. The semiconductor device of claim 1, further including:

back-side cap pads disposed on a bottom surface of the motherboard;

front-side cap pads disposed on a top surface of the motherboard and in direct contact with said capacitor terminals; and

vias between the back-side and front side cap pads for transferring heat applied to the back-side cap pad to the front-side cap pad.

8. The semiconductor device of claim 1, wherein the capacitor is located directly beneath the die load so that the distance between the capacitor affixed to the underside of the package and the die load affixed to the top surface of the package is minimized.

9. The semiconductor device of claim 1, further including at least one capacitor coupled to a top surface of the package and laterally spaced from the die load, said capacitor electrically coupled the package conductors and providing a third power source path for the die load.

10. A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard, said device further of a type having a spaced portion located between the motherboard and the package, the power shunt comprising:

a capacitor adapted to be positioned within the spaced portion between the motherboard and the package of the semiconductor device, said capacitor having a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer,

wherein said first type conductive layer and second type conductive layer are adapted to form a conductive bridge between the motherboard and the package.

11. The power shunt of claim 10, wherein said first type conductive layer is coupled to a different voltage source from the second type conductive layer in order to provide a capacitance between the two layers types.

12. The power shunt of claim 11, wherein said first type conductive layer is coupled to power source and said second conductive layer is coupled to a ground source.

13. The power shunt of claim 11, said capacitor including a plurality of conductive layers of a first type and a plurality of conductive layers of a second type electrically isolated from the layers of the first type by a plurality of dielectric layers.

14. The power shunt of claim 10, further including a terminals of a first type and a second type located along a first side of the capacitor and along an opposing side of the capacitor, said terminals coupled to respective type conductive layers of the capacitor.

15. A method for coupling a capacitor between an integrated circuit package and a motherboard having a die load disposed thereon, the method comprising:

electrically connecting a first source of capacitance to an underside of the package, wherein the first source of capacitance includes a first conductive layer, a second conductive layer, and a dielectric layer that electrically isolates the first conductive layer from the second conductive layer; and

electrically connecting the first conductive layer of the first source of capacitance and the second conductive layer to the motherboard so that the first and second conductive layers form a conductive bridge between the motherboard and the package.

16. The method of claim 15, wherein electrically connecting the first and second conductive layers to the motherboard include directly connecting the layers to a top surface of the motherboard.

17. The method of claim 15, further including disposing the first conductive layer, the second conductive layer, and the dielectric layer within the first source of capacitance oblique with respect to the underside of the package.

18. The method of claim 15, further including electrically connecting a second source of capacitance to a top surface of the package including an off-chip capacitor having a third conductive layer electrically connected to the first conductive layer, and a fourth conductive layer electrically connected to the second conductive layer.

19. The method of claim 15, further including:

forming contacts to a surface of the integrated circuit package, wherein at least one of the contacts electrically connects the first conductive layer to the surface and at least one other of the contacts electrically connects the second conductive layer to the surface; and

electrically connecting an integrated circuit to the contacts forming the die load.

20. The method of claim 15, further including disposing the first conductive layer, the second conductive layer, and the dielectric layer within the first source of capacitance parallel with respect to the underside of the package.