Method and structure for wafer-level reliability electromigration and stress migration test by isothermal heater

• US 20040124865A1
• Filed: 12/26/2002
• Published: 07/01/2004
• Est. Priority Date: 12/26/2002
• Status: Abandoned Application

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Chiu, Fu-Chien, Lin, Rueyway, Chuang, Kun Fu, Hwang, Jenn-Chang
• Application Number:
  US10/327,984
• Publication Number:
  US 20040124865A1
• Time in Patent Office: Days
• US Class Current: 324/760
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Due to the test current and the test temperature of the wafer-level reliability depend on each other in those conventional arts, the result of electromigration etc is not sure cause of the test current or the test temperature and debases the reliability of the test result. In the present invention, the electromigration test and the stress migration test of the wafer-level reliability are independently controlled, respectively. Therefore, the cause of electromigration and the stress migration can be sure resulting from the test current or the test temperature respectively. Furthermore, the isothermal heater of the present invention not only can keep a whole test wafer at a more uniform test temperature, but also can offset the electromagnetism resulted from the current of the isothermal heater by the arrangement of circuits thereof for reducing the effect of the electromagnetism.

Claims

1. A structure for wafer-level reliability, comprising:

an isothermal heater formed under a test wafer and a current provided in said isothermal heater for making said test wafer reach and maintain a test temperature; and

a measure apparatus measuring a temperature and electric characteristics of said test wafer when said test wafer reaches a test temperature.

2. The structure for wafer-level reliability according to claim 1, wherein a material of said isothermal heater is selected from the group consisting of polysilicon, silicon, copper, aluminum, tungsten and BaTiO₃.

3. The structure for wafer-level reliability according to claim 1, wherein a structure of said isothermal heater is a substrate structure.

4. The structure for wafer-level reliability according to claim 3, wherein a direction of said current in said isothermal heater and a direction of a current provided in said test wafer are opposite.

5. The structure for wafer-level reliability according to claim 1, wherein a structure of said isothermal heater is a sandwich structure comprising an upper heater and a lower heater that are formed above and under said test wafer respectively.

6. The structure for wafer-level reliability according to claim 5, wherein a direction of a current in said upper heater and a direction of a current in said lower heater are opposite.

7. The structure for wafer-level reliability according to claim 1, wherein a structure of said isothermal heater is a spiral structure.

8. The structure for wafer-level reliability according to claim 7, wherein said spiral structure of said isothermal heater is a spiral structure with two layers, an inner layer and outer layer.

9. The structure for wafer-level reliability according to claim 8, wherein a direction of a current in said inner layer and a direction of a current in said outer layer are opposite.

10. A structure for wafer-level reliability that employs a measure apparatus measuring a temperature and electric characteristics of said test wafer when said test wafer reaches a test temperature, comprising:

an isothermal heater formed under a test wafer and a current provided in said isothermal heater for making said test wafer reach and maintain said test temperature.

11. The structure for wafer-level reliability according to claim 10, wherein a structure of said isothermal heater is a substrate structure.

12. The structure for wafer-level reliability according to claim 10, wherein a structure of said isothermal heater is a sandwich structure comprising an upper heater and a lower heater that are formed above and under said test wafer respectively.

13. The structure for wafer-level reliability according to claim 10, wherein a structure of said isothermal heater is a spiral structure.

14. A method for wafer-level reliability electromigration and stress migration test, comprising:

forming an isothermal heater under a test wafer and providing a current in said isothermal heater for making said test wafer reach and maintain a test temperature; and

measuring a temperature and electric characteristics of said test wafer when said test wafer reaches a test temperature.

15. The method for wafer-level reliability electromigration and stress migration test according to claim 14, wherein a material of said isothermal heater is selected from the group consisting of polysilicon, silicon, copper, aluminum, tungsten and BaTiO₃.

16. The method for wafer-level reliability electromigration and stress migration test according to claim 14, wherein a structure of said isothermal heater is a substrate structure.

17. The method for wafer-level reliability electromigration and stress migration test according to claim 16, wherein a direction of said current in said isothermal heater and a direction of a current provided in said test wafer are opposite.

18. The method for wafer-level reliability electromigration and stress migration test according to claim 14, wherein a structure of said isothermal heater is a sandwich structure comprising an upper heater and a lower heater that are formed above and under said test wafer respectively.

19. The method for wafer-level reliability electromigration and stress migration test according to claim 18, wherein a direction of a current in said upper heater and a direction of a current in said lower heater are opposite.

20. The method for wafer-level reliability electromigration and stress migration test according to claim 14, wherein a structure of said isothermal heater is a spiral structure.

21. The method for wafer-level reliability electromigration and stress migration test according to claim 20, wherein said spiral structure of said isothermal heater is a spiral structure with two layers of an inner layer and an outer layer.

22. The method for wafer-level reliability electromigration and stress migration test according to claim 21, wherein a direction of a current in said inner layer and a direction of a current in said outer layer are opposite.