Apparatus for optimizing processor clock frequency in a hard disk drive to minimize power consumption while maximizing performance

• US 20040125498A1
• Filed: 04/14/2003
• Published: 07/01/2004
• Est. Priority Date: 12/27/2002
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Schmidt, Thorsten
• Granted Patent: US 7,072,138 B2
• Time in Patent Office: Days
• US Class Current: 360/78.04
• CPC Class Codes: G11B 21/083 on discs
• CPC Class Codes: G11B 5/5526 Control therefor; circuits, track configurations or relative disposition of servo-information transducers and servo-information tracks for control thereof G11B5/556 takes precedence

Abstract

Clock speed of the processor in a hard disk drive is controlled during run time to optimize the trade-off between minimizing power consumption and maximizing performance. Processor clock speed is increased during processing of code more performance critical to the disk drive system, while processor clock speed is reduced when less performance critical code is processed. An example of more critical code where processor clock speed is increased is the code executed by the processor from the start of a servo interrupt until output of resulting servo current command is provided from the processor to the actuator controller. To enable changing processor clock speed, an ASIC containing the disk drive processor is selected which provides the ability to switch clock rates of the processor during processor run time.

Claims

1. A storage apparatus comprising:

a rotatable disk;

a transducer;

an actuator that supports the transducer, the actuator configured to receive a signal controlling the actuator to move the transducer relative to the disk;

a processor coupled to transfer data to and from the magnetic media by the transducer and providing servo current command signals indicating actuator movement should occur; and

a clock signal generation circuit connected to selectively provide one of a plurality of different clock signals having different clock rates to the processor, wherein a first one of the clock signals is provided having a first clock rate when first code to cause an operation of the disk drive system is processed by the processor, and wherein a second one of the clock signals is provided having a second clock rate which is less than the first clock rate after the first code is processed to limit power consumption of the disk drive system.

2. The storage apparatus of claim 1,

wherein the first code ranges from initial receipt of a servo interrupt until a resulting servo current command signal is provided from the processor to cause movement of the actuator.

3. The storage apparatus of claim 1, wherein the clock signal generation circuit comprises:

a first phase locked loop configured for receiving a reference clock signal and generating the first clock signal having the first clock rate;

a second phase locked loop configured for receiving the reference clock signal and generating the second clock signal having the second clock rate; and

a clock controller connected to the first and second phase locked loops, the clock controller configured for selectively providing one of the first and second clock signals as the clock signal of the processor.

4. The storage apparatus of claim 3, wherein the clock controller is integrated with the processor.

5. The storage apparatus of claim 1, wherein the clock signal generation circuit comprises:

a phase locked loop having a clock signal input for connecting to an oscillator operating at a fixed frequency, the phase locked loop having a control input and an output, the control input for receiving a signal enabling the phase locked loop output to provide a clock signal at a predetermined frequency relative to the clock signal input; and

a clock controller connected to the phase locked loop, the clock controller providing the control input to the phase locked loop to selectively set the output clock frequency to one of the first and second clock rates.

6. The storage apparatus of claim 1,

wherein the first code ranges from receipt of a data request code, until a resulting track seeking servo current command signal is provided from the processor to control movement of the actuator.

7. The storage apparatus of claim 1, further comprising:

a memory for storing data which can be read by the processor, the data including code for causing the processor to select the first clock signal as a clock signal used by the processor when the first code is processed by the processor, and to select the second clock signal as a clock signal used by the processor after the resulting servo current command signal is provided from the processor.

8. The storage apparatus of claim 7, wherein the memory is a random access memory.

9. A disk drive system comprising:

a rotatable disk containing magnetic media with data recordable in defined tracks;

a transducer;

an actuator arm that supports the transducer;

a voice control motor (VCM) connected to the actuator arm to cause movement of the actuator arm, the VCM configured to receive a signal to move the actuator arm so that the transducer is moved relative to the disk;

processor coupled to receive servo data read from the magnetic media tracks using the transducer and to provide current command signals indicating actuator movement should occur;

a VCM control circuit configured to receive the servo current command signals from the processor and to provide current to the VCM in response to control movement of the actuator; and

a clock signal generation circuit connected to selectively provide one of a plurality of different clock signals having different clock rates to the processor, wherein a first one of the clock signals is provided having a first clock rate when a servo interrupt code is initially processed by the processor until a resulting servo current command signal is provided from the processor to the VCM control circuit, and wherein a second one of the clock signals is provided having a second clock rate less which is less than the first clock rate after the resulting servo current command signal is provided to the VCM control circuit to limit power consumption of the processor.

10. A disk drive system comprising:

a rotatable disk containing magnetic media with data recordable in defined tracks;

a transducer;

an actuator arm that supports the transducer;

a voice control motor (VCM) connected to the actuator arm to cause movement of the actuator arm, the VCM configured to receive a signal to move the actuator arm so that the transducer is moved relative to the disk;

a processor coupled to receive servo data read from the magnetic media tracks using the transducer and to provide servo current command signals indicating actuator movement should occur;

a VCM control circuit configured to receive the servo current command signals from the processor and to provide current to the VCM in response to control movement of the actuator; and

a clock signal generation circuit connected to selectively provide one of a plurality of different clock signals having different clock rates to the processor, wherein a first one of the clock signals is provided having a first clock rate when a data request code is initially processed by the processor until a resulting track seeking servo current command signal is provided from the processor to the VCM control circuit, and wherein a second one of the clock signals is provided having a second clock rate less which is less than the first clock rate after the resulting track seeking servo current command signal is provided by the processor.

11. A disk drive system comprising:

a processor coupled to read data from and writing data to a rotatable disk; and

a clock signal generating means for providing at least two different clock signals, each having a different clock rate, wherein a first one of the clock signals is provided to the processor when first code is processed, and wherein a second one of the clock signals is provided when second code is processed, wherein the second clock signal has a clock rate less than the first clock signal to limit power consumption of the processor.