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Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

  • US 20040125629A1
  • Filed: 12/31/2002
  • Published: 07/01/2004
  • Est. Priority Date: 12/31/2002
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising a memory array having at least one plane of memory cells formed above a substrate, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings.

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