Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

• US 20040125629A1
• Filed: 12/31/2002
• Published: 07/01/2004
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca, Nallamothu, Sucheta, Walker, Andrew J., Chen, En-Hsing, Ilkbahar, Alper, Petti, Christopher, Kouznetsov, Igor
• Granted Patent: US 7,505,321 B2
• Time in Patent Office: Days
• US Class Current: 365/17
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F² memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.

Claims

1. An integrated circuit comprising a memory array having at least one plane of memory cells formed above a substrate, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings.

2. The integrated circuit as recited in claim 1 wherein the memory array comprises a three-dimensional memory array having at least two planes of memory cells formed above the substrate.

3. The integrated circuit as recited in claim 1 wherein the memory cells comprise devices having a depletion mode threshold voltage at least some of the time.

4. The integrated circuit as recited in claim 1 wherein the modifiable conductance switch devices comprise transistors having a respective threshold voltage which is determined during manufacture.

5. The integrated circuit as recited in claim 1 wherein the modifiable conductance switch devices comprise transistors having a respective threshold voltage which is modifiable post-manufacture.

6. The integrated circuit as recited in claim 1 wherein the modifiable conductance switch devices comprise transistors having a charge storage dielectric.

7. The integrated circuit as recited in claim 6 wherein the charge storage dielectric of the memory cell transistors comprises an oxide-nitride-oxide (ONO) stack.

8. The integrated circuit as recited in claim 7 wherein the memory cell transistors have a depletion mode threshold voltage when the charge storage dielectric has a minimum stored charge level.

9. The integrated circuit as recited in claim 7 wherein the memory cell transistors have a first depletion mode threshold voltage corresponding to an erased data state and have a second depletion mode threshold voltage corresponding to a programmed data state.

10. The integrated circuit as recited in claim 7 wherein the memory cell devices have more than two nominal values of conductance, for storing more than one bit of data per memory cell.

11. The integrated circuit as recited in claim 1 wherein each string includes a first switch device at a first end thereof for coupling the string to an associated global array line.

12. The integrated circuit as recited in claim 11 wherein two NAND strings having word lines in common share a single global array line.

13. The integrated circuit as recited in claim 11 wherein each NAND string includes a second switch device at a second end thereof opposite the first end for coupling the string to an associated bias node.

14. The integrated circuit as recited in claim 13 wherein pairs of NAND strings are arranged so that a first control signal coupling one string of the pair to its associated global array line couples the other string of the pair to its associated bias node.

15. The integrated circuit as recited in claim 11 wherein the first switch device of each respective memory cell string comprises a transistor having a charge storage dielectric.

16. The integrated circuit as recited in claim 15 wherein the first switch device of each respective memory cell string has a depletion mode threshold voltage.

17. The integrated circuit as recited in claim 1 wherein the substrate comprises a monocrystalline substrate including circuitry which is coupled to the memory array.

18. The integrated circuit as recited in claim 1 wherein the substrate comprises a polycrystalline substrate.

19. The integrated circuit as recited in claim 1 wherein the substrate comprises an insulating substrate.

20. The integrated circuit as recited in claim 11 wherein the switch devices and memory cell devices forming each NAND string are structurally substantially identical.

21. The integrated circuit as recited in claim 2 wherein NAND strings on more than one memory level are respectively coupled to global array lines disposed on fewer levels than said more than one memory level.

22. The integrated circuit as recited in claim 2 wherein a respective plurality of NAND strings on each of at least two memory levels are coupled to a single global array line disposed on a single level of the integrated circuit.

23. An integrated circuit comprising:

a memory array having at least one plane of memory cells arranged in a plurality of series-connected NAND strings;

wherein each respective NAND string includes a first switch device at one end thereof for coupling the respective NAND string to an associated global array line, and further includes a second switch device at the other end thereof for coupling the respective NAND string to an associated bias node;

wherein the first switch device for a first NAND string and the second switch device for a second NAND string are responsive to a first control signal, and the second switch device for the first NAND string and the first switch device for the second NAND string are responsive to a second control signal; and

wherein the first and second NAND strings share word lines in common.

24. The integrated circuit as recited in claim 23 wherein:

the memory array comprises a two-dimensional memory array having one plane of memory cells formed in a substrate.

25. The integrated circuit as recited in claim 23 wherein:

the memory array comprises a three-dimensional memory array having more than one plane of memory cells formed above a substrate.

26. The integrated circuit as recited in claim 23 wherein:

the memory cells comprise transistors having a charge storage dielectric.

27. The integrated circuit as recited in claim 23 wherein:

the memory cells comprise transistors having a respective threshold voltage which is modifiable post-manufacture.

28. The integrated circuit as recited in claim 23 wherein:

the first and second switch devices of a given NAND string are structurally substantially identical to the memory cell transistors of the given NAND string.

29. The integrated circuit as recited in claim 23 wherein:

the memory cell transistors of a given NAND string have a depletion mode threshold voltage for at least one of two data states.

30. The integrated circuit as recited in claim 29 wherein:

the depletion mode threshold voltage for at least one of two data states is more negative than about −

0.5 volts.

31. An integrated circuit including a memory array arranged in a plurality of blocks, said integrated circuit comprising:

a first memory block comprising

a first bias node;

a second bias node;

a plurality of global bit lines traversing across the first block in a first direction;

a plurality of word lines traversing across the first block in a second direction different than the first direction;

a first block select line traversing across the first block generally parallel to and disposed on one side of the plurality of word lines;

a second block select line traversing across the first block generally parallel to and disposed on the other side of the plurality of word lines; and

a plurality of series-connected NAND strings, each comprising a first block select device responsive to the first block select line, a plurality of memory cell devices each responsive to a respective one of the plurality of word lines, and a second block select device responsive to the second block select line;

wherein the first block select device of each of a first group of the NAND strings is respectively coupled to a respective one of the plurality of global bit lines, and the first block select device of each of a second group of the NAND strings is respectively coupled to the first bias node; and

wherein the second block select device of each of the first group of the NAND strings is respectively coupled to the second bias node, and the second block select device of each of the second group of the NAND strings is respectively coupled to a respective one of the plurality of global bit lines.

32. The integrated circuit as recited in claim 31 wherein:

pairs of NAND strings are coupled to the same global bit line, each such pair including a NAND string from each of the first and second groups of NAND strings, thereby providing for a global bit line pitch which is half that of the NAND strings.

33. The integrated circuit as recited in claim 31 wherein:

more than one physically adjacent NAND strings of the first memory block share a contact to the first or second bias nodes.

34. The integrated circuit as recited in claim 31 wherein:

each NAND string of the first memory block contacts its associated global bit line by way of a via which is shared by a corresponding NAND string of another memory block having different word lines.

35. The integrated circuit as recited in claim 31 further comprising:

a second memory block disposed to one side of the first memory block, and sharing the first bias node and the plurality of global bit lines with the first memory block, said plurality of global bit lines traversing across the second block in the first direction, said second memory block respectively comprising a third bias node;

a second plurality of word lines traversing across the block in the second direction;

a third block select line traversing across the block generally parallel to and disposed on one side of the second plurality of word lines;

a fourth block select line traversing across the block generally parallel to and disposed on the other side of the second plurality of word lines; and

a second plurality of series-connected NAND strings, each respectively comprising a first block select device responsive to the third block select line, a plurality of memory cell devices each responsive to a respective one of the second plurality of word lines, and a second block select device responsive to the fourth block select line;

wherein the respective second block select device of each of a first group of the second plurality of NAND strings is respectively coupled to a respective one of the plurality of global bit lines, and the respective second block select device of each of a second group of the second plurality of NAND strings is respectively coupled to the first bias node; and

wherein the respective first block select device of each of the first group of the second plurality of NAND strings is respectively coupled to the third bias node, and the respective first block select device of each of the second group of the second plurality of NAND strings is respectively coupled to a respective one of the plurality of global bit lines.

36. The integrated circuit as recited in claim 35 wherein:

the first block select device of each of the first group of the NAND strings of the first memory block is respectively coupled to the respective one of the plurality of global bit lines by way of a contact which is shared by the respective second block select device of each of the first group of the second plurality of NAND strings for the second memory block.

37. The integrated circuit as recited in claim 31 wherein the memory array comprises a three-dimensional memory array having more than one memory levels formed above a substrate, said integrated circuit further comprising:

a third memory block disposed on a level of the memory array different than that of the first memory block, said first and third memory blocks sharing the plurality of global bit lines, the first bias node, and the second bias node, said third memory block respectively comprising

a third plurality of word lines traversing across the block in the second direction;

a fifth block select line traversing across the block generally parallel to and disposed on one side of the third plurality of word lines;

a sixth block select line traversing across the block generally parallel to and disposed on the other side of the third plurality of word lines; and

a third plurality of series-connected NAND strings, each respectively comprising a first block select device responsive to the fifth block select line, a plurality of memory cell devices each responsive to a respective one of the third plurality of word lines, and a second block select device responsive to the sixth block select line;

wherein the respective first block select device of each of a first group of the third plurality of NAND strings is respectively coupled to a respective one of the plurality of global bit lines, and the respective first block select device of each of a second group of the third plurality of NAND strings is respectively coupled to the first bias node; and

wherein the respective second block select device of each of the first group of the third plurality of NAND strings is respectively coupled to the second bias node, and the respective second block select device of each of the second group of the third plurality of NAND strings is respectively coupled to a respective one of the plurality of global bit lines.

38. The integrated circuit as recited in claim 37 wherein:

each NAND string of the first memory block contacts its associated global bit line by way of a via which is shared by a corresponding NAND string of the third memory block.

39. The integrated circuit as recited in claim 35 wherein:

each of the first group of NAND strings of the first memory block contacts its associated global bit line by way of a via which is shared by a NAND string of the second memory block.

40. The integrated circuit as recited in claim 31 wherein:

the memory cell devices comprise transistors having a charge storage dielectric.

41. The integrated circuit as recited in claim 31 wherein:

the memory cell devices comprise transistors having a respective threshold voltage which is modifiable post-manufacture.

42. The integrated circuit as recited in claim 40 wherein:

the first and second block select devices of a given NAND string are structurally identical to the memory cell transistors of the given NAND string.

43. The integrated circuit as recited in claim 40 wherein:

the memory cell transistors of a given NAND string have a depletion mode threshold voltage for at least one of two data states.

44. A method for operating an integrated circuit, said integrated circuit comprising a memory array having at least one plane of memory cells, said memory cells arranged in a plurality of series-connected NAND strings, said method comprising:

selecting a block of the array;

driving a first block select line for the selected block to a first block select voltage, said first block select line for coupling a first end of a first NAND string to a first global array line, and for coupling a first end of a second NAND string to a first bias node, said second NAND string sharing the same word lines as the first NAND string;

driving a second block select line for the selected block to a second block select voltage, said second block select line for coupling a second end of the first NAND string to a second bias node, and for coupling a second end of the second NAND string to the first global array line;

driving unselected word lines of the selected block to an unselected world line voltage;

driving at least one selected word line to a selected word line voltage;

impressing a first bias condition on the first bias node;

impressing a second bias condition on the second bias node; and

impressing a global array line bias voltage on the first global array line.

45. The method as recited in claim 44 wherein:

the first block select voltage, the second block select voltage, the global array line bias voltage, the first bias condition, and the second bias condition are chosen to couple the first end of the first NAND string to the first global array line, to couple the first end of the second NAND string to the first bias node, to couple the second end of the first NAND string to the second bias node, and to couple the second end of the second NAND string to the first global array line; and

the first block select voltage is substantially equal to the second block select voltage.

46. The method as recited in claim 45 wherein:

the unselected word line voltage is substantially equal to the first and second block select voltages;

the selected word line voltage is lower than the unselected word line voltage; and

the at least one selected word line is driven to the unselected word line voltage for a time before being driven to the selected word line voltage.

47. The method as recited in claim 46 wherein:

the global array line bias voltage, the first bias condition, and the second bias condition are chosen to impress a non-zero bias voltage across the first NAND string but not across the second NAND string.

48. The method as recited in claim 46 wherein:

the unselected word line voltage, the global array line bias voltage, the first bias condition, and the second bias condition are all chosen to be a substantially identical positive erase voltage;

the selected word line voltage is chosen to be substantially less than the erase voltage; and

all word lines of the selected block are selected, but are driven to the unselected word line voltage for a time before being driven to the selected word line voltage.

49. The method as recited in claim 44 wherein:

the first block select voltage, the second block select voltage, the global array line bias voltage, the first bias condition, and the second bias condition are chosen to couple the first end of the first NAND string to the first global array line, to couple the first end of the second NAND string to the first bias node, but to de-couple the second end of the first NAND string from the second bias node, and to de-couple the second end of the second NAND string from the first global array line.

50. The method as recited in claim 49 wherein:

the unselected word line voltage is within three volts of the first block select voltage;

the selected word line voltage is higher than the unselected word line voltage; and

the at least one selected word line is driven to the unselected word line voltage before being driven to the selected word line voltage.

51. A method for operating an integrated circuit memory array having at least one level of memory cells formed above a substrate, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings, said method comprising:

coupling a respective first end of two NAND strings to a global array line, both NAND strings sharing word lines in common; and

biasing the respective opposite ends of the two NAND strings to respective different voltages, such that a substantially greater bias voltage is developed across one of the NAND strings than the other.

52. The method as recited in claim 51 wherein:

the modifiable conductance switch devices comprise transistors having a charge storage dielectric.

53. The method as recited in claim 51 wherein:

the modifiable conductance switch devices comprise transistors having a respective threshold voltage which is modifiable post-manufacture.

54. A method for reading a memory cell in a memory array, said memory array having at least one plane of memory cells formed above an integrated circuit substrate, said memory cells comprising transistors having a charge storage dielectric arranged in a plurality of series-connected NAND strings, said method comprising:

selecting a block of the array, a NAND string within the selected block, and a memory cell within the selected NAND string;

coupling a first end of the selected NAND string to a global bit line and coupling a second end of the selected NAND string opposite the first end to a second shared bias node;

coupling a first end of a second NAND string to a first bias node, said second NAND string having word lines in common with the selected NAND string, and coupling a second end of the second NAND string opposite the first end to the global bit line;

impressing a first bias voltage onto the global bit line and a second bias voltage onto the second bias node to thereby impress a differential voltage across the selected NAND string;

impressing a read voltage onto a word line of the selected cell, said read voltage chosen to cause greater current flow through a respective cell for one data state than for a second data state;

impressing a passing voltage onto respective word lines of non-selected cells in the selected NAND string, said passing voltage chosen to cause substantially the same current to flow through a respective cell for both of the two data states;

impressing the first bias voltage onto the first shared bias node, thereby maintaining a substantially zero volt bias across the second NAND string; and

sensing current flow through the selected NAND string and onto the global bit line.

55. The method as recited in claim 54 further comprising:

driving a first block select line to a first block select voltage to simultaneously couple the first end of the selected NAND string to the global bit line and to couple the first end of the second NAND string to the first bias node; and

driving a second block select line to a second block select voltage to simultaneously couple the second end of the selected NAND string to the second shared bias node and to couple the second end of the second NAND string to the global bit line.

56. The method as recited in claim 54 wherein:

the passing voltage is substantially equal to the first bias voltage.

57. The method as recited in claim 54 wherein:

the read voltage is less than both the first and second bias voltages.

58. The method as recited in claim 54 wherein:

all word lines of the selected block are initially driven to the passing voltage, then the selected word line is driven to the read voltage.

59. The method as recited in claim 54 wherein:

substantially no bias voltage is impressed across memory cells in the second NAND string.

60. A method for reading a memory cell in a memory array, said memory array having at least one plane of memory cells formed above an integrated circuit substrate, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings, said method comprising:

selecting a block of the array, a NAND string within the selected block, and a memory cell within the selected NAND string;

coupling one end of the selected NAND string, and one end of a second NAND string, to a selected global bit line, said second NAND string sharing word lines in common with the selected NAND string;

impressing a read bias voltage across the selected NAND string;

impressing substantially no bias voltage across the second NAND string;

impressing a read voltage onto a word line associated with the selected cell, said read voltage chosen to cause greater current flow through a respective cell for one data state than for a second data state;

impressing a passing voltage onto respective word lines of non-selected cells in the selected NAND string, said passing voltage chosen to cause substantially the same current to flow through a respective cell for both of the two data states; and

sensing current flow through the selected NAND string onto the selected global bit line to determine the data state of the selected memory cell.

61. The method as recited in claim 60 wherein:

the passing voltage is chosen within the range of the bias voltage across the selected NAND string, thereby biasing non-selected memory cells in the selected NAND string with a voltage thereacross that is less than the bias voltage.

62. The method as recited in claim 60 further comprising:

ensuring that other NAND strings sharing the selected global bit line are de-coupled from the selected global bit line.

63. The method as recited in claim 60 wherein:

the modifiable conductance switch devices comprise transistors having a charge storage dielectric.

64. The method as recited in claim 60 wherein:

the modifiable conductance switch devices comprise transistors having a respective threshold voltage which is modifiable post-manufacture.

65. A method for programming a memory cell in a memory array, said memory array having at least one plane of memory cells formed above an integrated circuit substrate, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings, said method comprising:

selecting a block of the array, a NAND string within the selected block, and a memory cell within the selected NAND string;

coupling a first end of the selected NAND string to a global bit line;

coupling a first end of a second NAND string to a first bias node, said second NAND string having word lines in common with the selected NAND string;

de-coupling a second end of the selected NAND string from a second shared bias node;

de-coupling a second end of the second NAND string from the global bit line;

impressing a bit line programming voltage onto the global bit line to program the selected memory cell or a bit line inhibit voltage to inhibit programming of the selected memory cell;

impressing an inhibit bias voltage onto the first bias node;

driving unselected word lines of the selected block to a word line passing voltage; and

driving the selected word line to a word line programming voltage for a duration of time, to conditionally program the selected memory cell in accordance with the impressed global bit line voltage.

66. The method as recited in claim 65 further comprising:

driving the selected word line to the word line passing voltage for a time before driving the selected word line to the word line programming voltage.

67. The method as recited in claim 65 wherein:

the inhibit bias voltage is substantially the same as the bit line inhibit voltage.

68. The method as recited in claim 65 further comprising:

floating the second bias node.

69. The method as recited in claim 65 further comprising:

driving a first block select line to a first block select voltage to simultaneously couple the first end of the selected NAND string to the global bit line and to couple the first end of the second NAND string to the first bias node; and

driving a second block select line to a second block select voltage to simultaneously de-couple the second end of the selected NAND string from the second shared bias node and to de-couple the second end of the second NAND string from the global bit line.

70. The method as recited in claim 65 wherein:

the passing word line voltage is within about 2 volts of the inhibit bias voltage.

71. The method as recited in claim 65 further comprising:

after programming the selected memory cell, then programming the first and second block select devices in the first and second NAND strings to counteract any partial erase which may have occurred during programming of the selected memory cell.

72. The method as recited in claim 65 wherein:

the modifiable conductance switch devices comprise transistors having a charge storage dielectric.

73. The method as recited in claim 65 wherein:

the modifiable conductance switch devices comprise transistors having a respective threshold voltage which is modifiable post-manufacture.

74. A method for erasing a block in a memory array, said memory array having at least one plane of memory cells formed above an integrated circuit substrate, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings, said method comprising:

selecting a block of the array;

coupling a respective first end of each NAND string in the selected block to an associated global bit line;

coupling a respective second end of each NAND string in the selected block to an associated bias node;

impressing a source/drain erase voltage onto the global bit lines and the bias nodes associated with the selected block; and

impressing a word line erase voltage onto all word lines of the selected block for an erase time to erase the block.

75. The method as recited in claim 74 further comprising:

driving the word lines in the selected block to the source/drain erase voltage for a time before driving the word lines in the selected block to the word line erase voltage.

76. The method as recited in claim 75 further comprising:

driving all word lines and bias nodes for non-selected blocks to the source/drain erase voltage for the duration of the erase time.

77. The method as recited in claim 74 further comprising:

decreasing the source/drain erase voltage over the duration of the erase time from an initial source/drain erase voltage to a final source/drain erase voltage that is lower than the initial source/drain erase voltage.

78. The method as recited in claim 77 wherein:

the initial source/drain erase voltage is within the range from approximately 6 to 13 volts.

79. The method as recited in claim 74 wherein:

the word line erase voltage is substantially equal to ground.

80. The method as recited in claim 74 wherein:

the modifiable conductance switch devices comprise transistors having a charge storage dielectric.

81. The method as recited in claim 74 wherein:

the modifiable conductance switch devices comprise transistors having a respective threshold voltage which is modifiable post-manufacture.

82. A computer readable medium encoding an integrated circuit, said encoded integrated circuit comprising a memory array having at least one plane of memory cells formed above a substrate, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings.

83. The computer readable medium as recited in claim 82 wherein the encoded integrated circuit memory array comprises a three-dimensional memory array having at least two planes of memory cells.

84. The computer readable medium as recited in claim 82 wherein the encoded modifiable conductance switch devices comprise transistors having a charge storage dielectric.

85. The computer readable medium as recited in claim 82 wherein each encoded NAND string includes a first switch device at a first end thereof for coupling the string to an associated global array line.

86. The computer readable medium as recited in claim 85 wherein two NAND strings having word lines in common share a single global array line.

87. The computer readable medium as recited in claim 85 wherein each NAND string includes a second switch device at a second end thereof opposite the first end for coupling the string to an associated bias node.

88. The computer readable medium as recited in claim 87 wherein pairs of NAND strings are arranged so that a first control signal coupling one string of the pair to its associated global array line couples the other string of the pair to its associated bias node.

89. The computer readable medium as recited in claim 85 wherein the first switch device of each respective NAND string comprises a transistor having a charge storage dielectric.

90. The computer readable medium as recited in claim 89 wherein the first switch device of each respective memory cell string has a depletion mode threshold voltage.

91. The computer readable medium as recited in claim 85 wherein the switch devices and memory cell devices forming each NAND string are structurally substantially identical.

92. The computer readable medium as recited in claim 83 wherein NAND strings on more than one memory level are respectively coupled to global array lines disposed on fewer levels than said more than one memory level.

93. A computer readable medium encoding an integrated circuit layout, said encoded integrated circuit layout comprising:

a first memory block comprising

a plurality of channel stripes running in a first direction;

a plurality of gate stripes running in a second direction different than the first direction, said gate stripes forming a plurality of word lines, a first block select line running generally parallel to and disposed on one side of the plurality of word lines, and a second block select line running generally parallel to and disposed on the other side of the plurality of word lines;

a plurality of global bit lines traversing across the first block in the first direction;

wherein said plurality of gate stripes and said plurality of channel stripes together form a plurality of series-connected NAND strings, each comprising a first block select device coupled to the first block select line, a plurality of memory cell devices each coupled to a respective one of the plurality of word lines, and a second block select device coupled to the second block select line;

wherein the first block select device of each of a first group of the NAND strings is respectively coupled to a respective one of the plurality of global bit lines, and the first block select device of each of a second group of the NAND strings is respectively coupled to a first bias node; and

wherein the second block select device of each of the first group of the NAND strings is respectively coupled to a second bias node, and the second block select device of each of the second group of the NAND strings is respectively coupled to a respective one of the plurality of global bit lines.

94. The computer readable medium as recited in claim 93 wherein:

pairs of NAND strings are coupled to the same global bit line, each such pair including a NAND string from each of the first and second groups of NAND strings, thereby providing for a global bit line pitch which is half that of the NAND strings.

95. The computer readable medium as recited in claim 93 wherein:

more than one physically adjacent NAND strings of the first memory block share a contact to the first or second bias nodes.

96. The computer readable medium as recited in claim 93 wherein:

the first group and second group of NAND strings are 2;

1 interleaved.

97. The computer readable medium as recited in claim 93 wherein:

the first group and second group of NAND strings are 4;

1 interleaved.

98. The computer readable medium as recited in claim 93 wherein:

each NAND string of the first memory block contacts its associated global bit line by way of a via which is shared by a corresponding NAND string of another memory block having different word lines.

99. The computer readable medium as recited in claim 93 further comprising:

a second memory block disposed to one side of the first memory block, and sharing the first bias node and the plurality of global bit lines with the first memory block, said plurality of global bit lines traversing across the second block in the first direction.

100. The computer readable medium as recited in claim 99 wherein:

each of the first group of NAND strings of the first memory block contacts its associated global bit line by way of a via which is shared by a NAND string of the second memory block.

101. The computer readable medium as recited in claim 93 wherein the channel stripes are formed on a dielectric layer disposed above a substrate for the integrated circuit.

102. The computer readable medium as recited in claim 93 wherein the memory array comprises a three-dimensional memory array having more than one memory levels formed above a substrate, said integrated circuit further comprising:

a third memory block disposed on a level of the memory array different than that of the first memory block, said first and third memory blocks sharing the plurality of global bit lines, the first bias node, and the second bias node.

103. The computer readable medium as recited in claim 102 wherein:

each NAND string of the first memory block contacts its associated global bit line by way of a via which is shared by a corresponding NAND string of the third memory block.

104. The computer readable medium as recited in claim 93 wherein:

the first and second block select devices of a given NAND string are structurally identical to the memory cell transistors of the given NAND string.

105. A memory cell comprising a TFT SONOS transistor having a depletion-mode threshold voltage for at least one of two data states.

106. A memory cell as recited in claim 105 wherein the depletion mode threshold voltage for at least one data state is no greater than −

0.5 volts.

107. A memory cell as recited in claim 105 wherein the depletion mode threshold voltage for each of two data states is no greater than 0 volts.

108. An integrated circuit comprising a three-dimensional memory array having at least two planes of memory cells formed above a substrate, said memory cells of each plane arranged in a plurality of series-connected NAND strings.

109. The integrated circuit as recited in claim 108 further comprising:

a plurality of global array lines disposed on a layer of the integrated circuit, each of which is shared by at least one NAND string on each of at least two memory planes.

110. The integrated circuit as recited in claim 109 wherein at least two NAND strings on each of at least two memory planes make contact to an associated global array line by way of a shared zia.

111. The integrated circuit as recited in claim 108 wherein the memory cells comprise transistors having a charge storage dielectric layer.

112. The integrated circuit as recited in claim 108 wherein the charge storage dielectric layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) stack.

113. The integrated circuit as recited in claim 111 wherein the memory cell transistors have a depletion mode threshold voltage for at least one of two data states which is no greater than −

0.5 volts.

114. The integrated circuit as recited in claim 111 wherein the memory cell transistors have a respective depletion mode threshold voltage for each of two data states, each of which is no greater than 0 volts.