OPTION FUSE CIRCUIT USING STANDARD CMOS MANUFACTURING PROCESS
First Claim
1. An option fuse circuit manufactured with standard CMOS manufacturing processes, comprising:
- a latch comprising a first node and a second node, and being used for latching signals at the first and the second nodes;
a comparator comprising two input nodes and an output node, wherein the two input nodes are electrically connected to the first and the second nodes respectively, the comparator being used for inputting the signals at the first and the second nodes respectively, and outputting a comparison signal by comparing the two signals;
a first logic cell for storing a non-volatile data, comprising a first word line node and a first bit line node, wherein the first word line node is electrically connected to the output node of the comparator in order to input the comparison signal, the first bit line node being electrically connected to the first node; and
a second logic cell for storing a non-volatile data, comprising a second word line node and a second bit line node, wherein the second word line node is electrically connected to the output node of the comparator in order to input the comparison signal, the second bit line node being electrically connected to the second node;
wherein the data stored in the first logic cell and the data stored in the second logic cell are complementary to each other.
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Accused Products
Abstract
An option fuse circuit using standard CMOS manufacturing processes includes a latch for latching signals, which includes a first node and a second node. The option fuse circuit also includes a comparator, which includes two input nodes and an output node. The comparator receives signals input at the two input nodes from the first and the second nodes, and compares the two signals in order to output a comparison signal. The option fuse circuit further includes two logic cells for storing non-volatile data. The logic cells include a word line node and a bit line node. The word line nodes are electrically connected to the output node of the comparator, while the bit line nodes are electrically connected to the first and the second nodes, respectively.
5 Citations
17 Claims
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1. An option fuse circuit manufactured with standard CMOS manufacturing processes, comprising:
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a latch comprising a first node and a second node, and being used for latching signals at the first and the second nodes;
a comparator comprising two input nodes and an output node, wherein the two input nodes are electrically connected to the first and the second nodes respectively, the comparator being used for inputting the signals at the first and the second nodes respectively, and outputting a comparison signal by comparing the two signals;
a first logic cell for storing a non-volatile data, comprising a first word line node and a first bit line node, wherein the first word line node is electrically connected to the output node of the comparator in order to input the comparison signal, the first bit line node being electrically connected to the first node; and
a second logic cell for storing a non-volatile data, comprising a second word line node and a second bit line node, wherein the second word line node is electrically connected to the output node of the comparator in order to input the comparison signal, the second bit line node being electrically connected to the second node;
wherein the data stored in the first logic cell and the data stored in the second logic cell are complementary to each other. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification