Wide frequency range delay locked loop

• US 20040125905A1
• Filed: 12/31/2002
• Published: 07/01/2004
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Haerle, Dieter, Vlasenko, Peter
• Granted Patent: US 7,336,752 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range

Abstract

A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Claims

1. A delay locked loop comprising:

a digital delay circuit which enables delay elements to provide coarse phase adjustment in the delay locked loop; and

an analog delay circuit which provides a fine phase adjustment in the delay locked loop while the digital delay circuit is held at a fixed delay.

2. The delay locked loop of claim 1 further comprising:

a lock detector in the digital delay circuit which detects completion of the coarse phase adjustment, freezes the fixed delay upon completion and enables fine phase adjustment.

3. The delay locked loop of claim 1 wherein the digital delay circuit operates over a wide delay range.

4. The delay locked loop of claim 3 wherein the analog delay circuit operates over a small delay range within the wide delay range.

5. The delay locked loop of claim 1 wherein the analog delay circuit is held at a second fixed delay until the digital delay circuit completes the coarse phase adjustment.

6. The delay locked loop of claim 1 wherein the digital delay circuit includes a plurality of fixed delay elements.

7. A method for performing phase adjustment in a delay locked loop comprising the steps of:

enabling delay elements in a digital delay circuit to provide coarse phase adjustment in the delay locked loop; and

providing a fine phase adjustment with an analog delay circuit in the delay locked loop while the digital delay circuit is held at a fixed delay.

8. The method of claim 7 further comprising the steps of:

detecting completion of the coarse phase adjustment;

freezing the fixed delay upon completion; and

enabling fine phase adjustment.

9. The method of claim 7 wherein the digital delay circuit operates in a wide delay range.

10. The method of claim 9 wherein the analog delay circuit operates in a small delay range within the wide delay range.

11. The delay locked loop of claim 7 further comprising the step of:

holding the analog delay circuit at a second fixed delay until the digital delay circuit completes the coarse phase adjustment.

12. The delay locked loop of claim 7 wherein the digital delay circuit includes a plurality of fixed delay elements.

13. A delay locked loop comprising:

digital delay means for enabling delay elements to provide coarse phase adjustment in the delay locked loop; and

analog delay means for providing a fine phase adjustment in the delay locked loop while the digital delay circuit is held at a fixed delay.

14. The delay locked loop of claim 13 wherein the digital delay means further comprise:

lock detection means for detecting completion of the coarse phase adjustment, freezing the fixed delay upon completion and enabling the fine phase adjustment.

15. The delay locked loop of claim 13 wherein the digital delay means operate in a wide delay range.

16. The delay locked loop of claim 15 wherein the analog delay means operate in a small delay range within the wide delay range.

17. The delay locked loop of claim 13 wherein the analog delay means is held at a second fixed delay until the digital delay means completes the coarse phase adjustment.

18. The delay locked loop of claim 13 wherein the digital delay circuit includes a plurality of fixed delay elements.

19. A delay locked loop comprising:

a digital delay circuit which provides coarse delay adjustment until a locked condition has been attained by the delay locked loop; and

an analog delay circuit which provides fine delay adjustment to maintain the delay locked loop substantially in the locked condition, the digital delay circuit being maintained at a fixed delay once the analog delay circuit is activated.