Chip on board and heat sink attachment methods

• US 20040126931A1
• Filed: 07/22/2003
• Published: 07/01/2004
• Est. Priority Date: 09/03/1998
• Status: Active Grant

• Current Assignee: David R. Hembree
• Original Assignee: David R. Hembree
• Inventors: Hembree, David R.
• Granted Patent: US 7,244,637 B2
• Time in Patent Office: Days
• US Class Current: 438/122
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85002 being a removable or sacrificial coating
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A process for forming a thermally enhanced Chip On Board semiconductor device (10) with a heat sink (30) is described. In one aspect, a thermally conducting filled gel elastomer material (50) or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface (18) to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material (38) which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die.

Claims

1. An assembly method for a Chip On Board semiconductor device having a semiconductor die having a heat sink cap abutting a portion of the top surface of a substrate including:

placing a compliant adhesive filled gel silicone elastomer between a portion of an upper surface of said semiconductor die and a portion of a lower surface of said heat sink cap;

pressing said semiconductor die into said cap to engage said die and cap in compliant removable adhesion and for the edge of the cap to abut the substrate; and

injecting an encapsulant into said heat sink cap engaging at least interior portions of said heat sink cap, at least portions of said semiconductor die, at least portions of an upper surface of said substrate, and at least portions of said filled gel silicone elastomer.

2. The method of claim 1, wherein said compliant adhesive filled gel elastomer includes a cross-linked silicone.

3. An assembly method for a Chip On Board semiconductor device having a semiconductor die contained within a portion of a cap having a lower edge abutting a portion of a top surface of a substrate comprising:

positioning a compliant adhesive filled gel silicone elastomer between said semiconductor die and said cap;

pressing said semiconductor die into said cap causing removable adhesion of said semiconductor die and said cap and causing the lower edge of said cap to abut said substrate; and

injecting an encapsulant into said cap engaging at least interior portions of said cap, at least portions of said semiconductor die, at least portions of an upper surface of said substrate, and at least portions of said filled gel silicone elastomer.

4. The method of claim 3, wherein said adhesive filled gel elastomer includes a metal filled cross-linked silicone.