Methods of forming electronic components, and a conductive line
First Claim
1. A semiconductor processing method comprising:
- forming first and second layers over a substrate, the second layer having a higher oxidation rate than the first layer when exposed to an oxidizing atmosphere, the substrate having a periphery, the first layer having an exposed first outer edge spaced inside the substrate periphery, the second layer having an exposed first outer edge spaced inside the substrate periphery;
etching into the second layer first edge at a faster rate than any etching into the first layer first edge and forming an exposed second outer edge of the second layer; and
after the etching, exposing the substrate to the oxidizing atmosphere with the second layer second outer edge exposed and forming an oxidized first layer edge.
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Abstract
In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the substrate periphery. Etching is conducted into the higher oxidation rate material at a faster rate than any etching which occurs into the lower oxidation rate material. Then, the substrate is exposed to the oxidizing atmosphere. In another implementation, a stack of at least two conductive layers for an electronic component is formed. The two conductive layers have different oxidation rates when exposed to an oxidizing atmosphere. The layer with the higher oxidation rate has an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate. The stack is exposed to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers. In yet another implementation, a transistor comprises a semiconductive substrate and a gate stack formed thereover. The stack in at least one cross section defines a channel length within the substrate of less than 1 micron, with the stack comprising conductive material formed over a gate dielectric layer. An insulative layer is formed on outer lateral edges of the conductive material, with such layer having opposing substantially continuous straight linear outer lateral edges over all conductive material of the gate stack within the one cross section.
49 Citations
47 Claims
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1. A semiconductor processing method comprising:
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forming first and second layers over a substrate, the second layer having a higher oxidation rate than the first layer when exposed to an oxidizing atmosphere, the substrate having a periphery, the first layer having an exposed first outer edge spaced inside the substrate periphery, the second layer having an exposed first outer edge spaced inside the substrate periphery;
etching into the second layer first edge at a faster rate than any etching into the first layer first edge and forming an exposed second outer edge of the second layer; and
after the etching, exposing the substrate to the oxidizing atmosphere with the second layer second outer edge exposed and forming an oxidized first layer edge. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor processing method comprising:
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forming a stack of at least two conductive layers for an electronic component over a substrate, the two conductive layers having different oxidation rates when exposed to an oxidizing atmosphere, the layer with the higher oxidation rate having an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate; and
exposing the stack of conductive layers to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method of forming an electronic component comprising:
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forming first and second conductive materials over a substrate, the second material having a higher oxidation rate than an oxidation rate of the first material when exposed to an oxidizing atmosphere;
first etching the first and second conductive materials to form a conductive component, the conductive component having opposing substantially continuous straight linear outer lateral edges of the first and second conductive materials;
second etching into the second material outer lateral edges to recess them inside of the first material outer lateral edges; and
after the second etching, exposing the substrate to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second conductive materials. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A semiconductor processing method of forming a transistor comprising:
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forming a gate dielectric layer, a doped silicon layer, a silicide layer and an insulating layer over a channel region of a substrate, the silicide layer having a higher oxidation rate than oxidation rates of the doped silicon layer and the insulating layer when exposed to an oxidizing atmosphere;
first etching the insulating layer, the silicide layer and the doped silicon layer to form a conductive gate stack having an insulating cap over the channel region, the gate stack having two opposing and respectively linearly aligned outer lateral edges of the insulating, silicide and doped silicon layers;
second etching the silicide layer substantially selectively relative to the insulating cap and the doped silicon layer to recess outer lateral edges of the silicide layer to within outer lateral edges of both the insulating and doped silicon layers of the gate stack;
after the second etching, exposing the substrate to the oxidizing atmosphere effective to grow an oxide layer over outer lateral edges of the silicide and doped silicon layers;
after the exposing, first implanting a dopant impurity into the substrate proximate the gate stack to form at least one of an LDD region or a halo region;
after the first implanting, forming insulative material over the oxide layer; and
after forming the insulative material, second implanting a dopant impurity into the substrate proximate the gate stack to form transistor source/drain regions. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38)
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39. A transistor comprising:
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a semiconductive substrate;
a stack of a gate dielectric layer over the semiconductive substrate, a first conductive layer over the gate dielectric layer, a second conductive layer different in composition from the first and received over the first, and an insulative cap over the second conductive layer;
the first conductive layer of the stack having opposing outer lateral edges which are spaced less than one micron apart defining a channel length within the semiconductive substrate of less than one micron, the second conductive layer of the gate stack having opposing outer lateral edges which are spaced apart less than the opposing outer lateral edges of the first conductive layer are spaced apart; and
an oxide layer formed over the outer lateral edges of the first conductive layer, the second conductive layer and the insulative cap, the oxide layer having opposing substantially continuous straight linear outer lateral edges over the insulating cap, the first conductive layer and the second conductive layer. - View Dependent Claims (40, 41, 42)
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43. A transistor comprising:
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a semiconductive substrate;
a gate stack formed over the semiconductive substrate and defining in at least one cross section a channel length within the semiconductive substrate of less than 1 micron, the gate stack comprising conductive material formed over a gate dielectric layer; and
an insulative layer formed on outer lateral edges of the conductive material, the insulative layer having opposing substantially continuous straight linear outer lateral edges over all conductive material of the gate stack within the one cross section. - View Dependent Claims (44, 45, 46, 47)
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Specification