Refresh port for a dynamic memory
2 Assignments
0 Petitions
Accused Products
Abstract
A refresh port for a dynamic memory. In one embodiment, an apparatus includes a memory and a refresh command interface to receive a refresh command including a portion indicating signal. Refresh logic performs a refresh to a portion of the memory array specified, at least partially, by the portion specifying signal. Data transfer interfaces receive data transfer commands and transfer memory to and from the apparatus. Another apparatus includes refresh control logic to output a refresh signal and a portion specifying signal via a refresh command interface.
-
Citations
39 Claims
- 1. A dynamic random access memory (DRAM) refresh port.
-
7. An apparatus comprising:
-
a memory array;
a refresh command interface to receive a refresh command including a portion specifying signal;
refresh logic to refresh a portion of said memory array specified by the portion specifying signal in response to the refresh command;
a plurality of data transfer interfaces to receive data transfer commands and to transfer memory data to and from the apparatus. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. An apparatus comprising:
-
a plurality of data transfer interfaces to output data transfer requests and to transfer memory data to and from the apparatus;
a refresh command interface;
refresh control logic to output a refresh signal and a portion specifying signal via the refresh command interface. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
-
-
22. A method comprising:
-
providing commands defining a memory request via a command interface;
providing refresh commands specifying portions to refresh to a memory array via a refresh port. - View Dependent Claims (23, 24, 25, 26, 27)
-
-
28. A method comprising:
-
receiving a memory access command via a command interface;
receiving a refresh command via a refresh interface;
refreshing a row of memory specified by the refresh command in response to the refresh command. - View Dependent Claims (29, 30)
-
-
31. A system comprising:
-
a first device having a memory request interface and a refresh output port;
a memory device comprising a memory array, the memory device being coupled to the first device, the memory array having a refresh input port coupled to the refresh output port, the memory device to refresh memory cells at least partially specified by refresh commands in response to refresh commands received from the first device via the refresh output port and the refresh input port. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39)
-
Specification