Memory reclamation

• US 20040128464A1
• Filed: 12/30/2002
• Published: 07/01/2004
• Est. Priority Date: 12/30/2002
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: MacKey, Richard P., Murray, Joseph, Schmisseur, Mark A., Goldschmidt, Marc A., Lee, Micheil J.
• Application Number:
  US10/331,843
• Publication Number:
  US 20040128464A1
• Time in Patent Office: Days
• US Class Current: 711/171
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Embodiments of the present invention provide for configurable memory bus width and memory reclamation. In particular, the memory controller is configured to use a width of memory that is less than that fully available such that back-to-back writes can occur, as opposed to read-modify-writes. Unused regions of memory (defined by the total available memory width subtracted by the managed memory width) are partially or fully reclaimed, thus increasing the effective memory size available to the user. The configuration methods accommodate multiple interface bus widths while maintaining bandwidth not previously possible.

Claims

1. A method for providing a configurable memory data width, comprising:

determining a data width supported by a device;

determining a data width supported by a region of memory;

mapping data from the device to a first sub-region of the memory;

reclaiming an unused sub-region of memory and configuring it as a second sub-region of memory; and

mapping the second sub-region of memory as another parallel memory region.

6. The method claimed in claim 1, wherein the memory comprises a 64-bit SDRAM and the bus comprises a 32-bit internal bus.

7. The method claimed in claim 1, further comprising:

configuring a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory.

2. The method claimed in claim 2, further comprising:

storing error correction data for data mapped in the first sub-region in parallel to the data in an error correction region of memory.

3. The method claimed in claim 2, further comprising:

storing error correction data for data mapped in the second sub-region within the second sub-region of data.

4. The method claimed in claim 3, wherein the memory comprises a memory having a plurality of banks.

5. The method claimed in claim 4, wherein the first sub-region comprises a region of a bank of memory.

8. A machine readable medium having stored therein a plurality of machine readable instructions executable by a processor to provide a configurable memory data width, comprising:

instructions to determine a data width supported by a device;

instructions to determine a data width supported by a region of memory;

instructions to map data from the device to a first sub-region of memory;

instructions to reclaim an unused sub-region of memory and configuring it as a second sub-region of memory; and

instructions to map the second sub-region of memory as another parallel memory region.

9. The machine readable medium claimed in claim 8, further comprising:

instructions to store error correction data for data mapped in the first sub-region in parallel to the data in an error correction region of memory.

10. The machine readable medium claimed in claim 9, further comprising:

instructions to store error correction data for data mapped in the second sub-region within the second sub-region of data.

11. The machine readable medium claimed in claim 10, wherein the memory comprises a memory having a plurality of banks.

12. The machine readable medium claimed in claim 11, wherein the first sub-region comprises a region of a bank of memory.

13. The machine readable medium claimed in claim 12, wherein the memory comprises a 64-bit SDRAM and the bus comprises a 32-bit internal bus.

14. The machine readable medium claimed in claim 8, further comprising:

instructions to configure a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory.

15. An apparatus for providing a configurable memory data width, comprising:

a device supporting a first data width;

a memory supporting a second data width; and

a controller in communication with the device and memory, wherein the controller maps data from the device to a first sub-region of the memory, reclaims an unused sub-region of memory, configures the unused sub-region of memory as a second sub-region of memory, and maps the second sub-region of memory as another memory region.

16. The apparatus claimed in claim 15, wherein the controller stores error correction data for data mapped in the first sub-region in parallel to the data in an error correction region of memory.

17. The apparatus claimed in claim 16, wherein the controller stores error correction data for data mapped in the second sub-region within the second sub-region of data.

18. The apparatus claimed in claim 17, wherein the memory comprises a memory having a plurality of banks.

19. The apparatus claimed in claim 18, wherein the first sub-region comprises a region of a bank of memory.

20. The apparatus claimed in claim 19, wherein the memory comprises a 64-bit SDRAM and the bus comprises a 32-bit internal bus.

21. The apparatus claimed in claim 25, wherein the controller configures a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory, and maps data from the device to the configured first sub-region of the memory.