Configurable memory bus width

• US 20040128465A1
• Filed: 12/30/2002
• Published: 07/01/2004
• Est. Priority Date: 12/30/2002
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lee, Micheil J., Murray, Joseph, Mackey, Richard P., Schmisseur, Mark A., Goldschmidt, Marc A.
• Application Number:
  US10/331,860
• Publication Number:
  US 20040128465A1
• Time in Patent Office: Days
• US Class Current: 711/171
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution

Abstract

A method and apparatus for providing a configurable memory data width including a device supporting a first data width, a memory supporting a second data width, and a controller. The controller configures a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory, and maps data from the device to the configured first sub-region of the memory. The controller implements a constant in an unused region of the memory, and calculates error correction data based upon the data mapped in the sub-region of the memory and the constant value in the unused region of the memory.

Claims

1. A method for providing a configurable memory data width, comprising:

determining a data width supported by a device;

determining a data width supported by a region of memory;

configuring a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory; and

mapping data from the device to the configured first sub-region of the memory.

2. The method claimed in claim 1, wherein configuring a first sub-region of the memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory, further comprises:

configuring a first sub-region of the memory having a data width less than that fully available when the data width supported by the device is less than the data width supported by the region of memory.

3. The method claimed in claim 2, wherein configuring a first sub-region of the memory having a data width less than that fully available when the data width supported by the device is less than the data width supported by the region of memory, further comprises:

configuring a first sub-region of the memory having a data width that matches the data width supported by the device.

4. The method claimed in claim 1, wherein the memory comprises a memory having a plurality of banks.

5. The method claimed in claim 4, wherein the first sub-region comprises a region of a bank of memory.

6. The method claimed in claim 1, wherein the memory comprises a 64-bit SDRAM and the bus comprises a 32-bit internal bus.

7. The method claimed in claim 1, further comprising:

bursting data to each successive address location in the first sub-region of memory.

8. The method claimed in claim 1, further comprising:

calculating error correction data for the data.

9. The method claimed in claim 3, wherein calculating error correction data for the data, further comprises:

implementing a constant in an unused region of the memory; and

calculating error correction data based upon the data mapped in the sub-region of the memory and the constant value in the unused region of the memory.

10. A machine readable medium having stored therein a plurality of machine readable instructions executable by a processor to provide a configurable memory data width, comprising:

instructions to determine a data width supported by a device;

instructions to determine a data width supported by a region of memory;

instructions to configure a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory; and

instructions to map data from the device to the configured first sub-region of the memory.

11. The machine readable medium claimed in claim 10, wherein instructions to configure a first sub-region of the memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory, further comprises:

instructions to configure a first sub-region of the memory having a data width less than that fully available when the data width supported by the device is less than the data width supported by the region of memory.

12. The machine readable medium claimed in claim 11, wherein instructions to configure a first sub-region of the memory having a data width less than that fully available when the data width supported by the device is less than the data width supported by the region of memory, further comprises:

instructions to configure a first sub-region of the memory having a data width that matches the data width supported by the device.

13. The machine readable medium claimed in claim 10, wherein the memory comprises a memory having a plurality of banks.

14. The machine readable medium claimed in claim 13, wherein the first sub-region comprises a region of a bank of memory.

15. The machine readable medium claimed in claim 10, wherein the memory comprises a 64-bit SDRAM and the bus comprises a 32-bit internal bus.

16. The machine readable medium claimed in claim 10, further comprising:

instructions to burst data to each successive address location in the first sub-region of memory.

17. The machine readable medium claimed in claim 10, further comprising:

instructions to calculate error correction data for the data.

18. The machine readable medium claimed in claim 12, wherein instructions to calculate error correction data for the data, further comprises:

instructions to implement a constant in an unused region of the memory; and

instructions to calculate error correction data based upon the data mapped in the sub-region of the memory and the constant value in the unused region of the memory.

19. An apparatus for providing a configurable memory data width, comprising:

a device supporting a first data width;

a memory supporting a second data width; and

a controller in communication with the device and memory, wherein the controller configures a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory, and maps data from the device to the configured first sub-region of the memory.

20. The apparatus claimed in claim 19, wherein the controller configures a first sub-region of the memory having a data width less than that fully available when the data width supported by the device is less than the data width supported by the region of memory.

21. The apparatus claimed in claim 20, wherein the controller configures a first sub-region of the memory having a data width that matches the data width supported by the device.

22. The apparatus claimed in claim 19, wherein the memory comprises a memory having a plurality of banks.

23. The apparatus claimed in claim 22, wherein the first sub-region comprises a region of a bank of memory.

24. The apparatus claimed in claim 19, wherein the memory comprises a 64-bit SDRAM and the bus comprises a 32-bit internal bus.

25. The apparatus claimed in claim 19, wherein the controller bursts data to each successive address location in the first sub-region of memory.

26. The apparatus claimed in claim 19, wherein the controller calculates error correction data for the data.

27. The apparatus claimed in claim 21, wherein the controller implements a constant in an unused region of the memory, and calculates error correction data based upon the data mapped in the sub-region of the memory and the constant value in the unused region of the memory.