Method for optimizing processor clock frequency in a hard disk drive to minimize power consumption while maximizing performance

• US 20040128575A1
• Filed: 04/14/2003
• Published: 07/01/2004
• Est. Priority Date: 12/27/2002
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Schmidt, Thorsten
• Granted Patent: US 7,089,432 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3221 of disk drive devices
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Clock speed of the processor in a hard disk drive is controlled during run time to optimize the trade-off between minimizing power consumption and maximizing performance. Processor clock speed is increased during processing of code more performance critical to the disk drive system, while processor clock speed is reduced when less performance critical code is processed. An example of more critical code where processor clock speed is increased is the code executed by the processor from the start of a servo interrupt until output of resulting servo current command is provided from the processor to the actuator controller. To enable changing processor clock speed, an ASIC containing the disk drive processor is selected which provides the ability to switch clock rates of the processor during processor run time.

Claims

1. A method of controlling power consumption in a disk drive, the method comprising the steps of:

controlling clock speed of a processor to operate at a first rate when the processor processes first code to control an operation of the disk drive; and

controlling clock speed of the processor to operate at a second rate when the processor is processing second code to limit power consumption of the processor.

2. The method of claim 1 wherein the first code comprises code starting from a start of a servo interrupt until a servo current command signal is provided from the processor to a hard disk controller to control position of the actuator.

3. The method of claim 1 wherein the first code comprises code ranging from a start of a data read code to code executed to cause a current command signal to be provided from a processor to a hard disk controller to cause a track seeking operation.

4. The method of claim 1 wherein the second rate is applied when servo information is processed enabling the processor to set up for receipt of subsequent servo data.