Methods implementing multiple interfaces for a storage device using a single ASIC

• US 20040128627A1
• Filed: 04/21/2003
• Published: 07/01/2004
• Est. Priority Date: 12/27/2002
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Zayas, Fernando A.
• Application Number:
  US10/419,540
• Publication Number:
  US 20040128627A1
• Time in Patent Office: Days
• US Class Current: 716/1
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Methods for producing and using a single application specific integrated circuit (ASIC) die, to support multiple interfaces for rotating media storage devices, are provided. At least two different interfaces for storage devices including rotatable storage medium are compared. Elements that are common to the different interfaces are identified. Elements that are unique to the different interfaces are also identified. The unique elements for each of the different interfaces, and the common elements, are incorporated into a single ASIC die. Switching is implemented within the single ASIC die, such that the common elements are used regardless of which one of the different interfaces is being used, and the unique elements are used based on which one of the different interfaces is being used.

Claims

1. A method for producing a single application specific integrated circuit (ASIC) die capable of supporting multiple interfaces for rotating media storage devices, comprising:

(a) comparing at least two different interfaces for storage devices including rotatable storage medium;

(b) identifying elements that are common to the different interfaces;

(c) identifying elements that are unique to the different interfaces;

(d) incorporating the unique elements for each of the different interfaces, and the common elements, into a single ASIC die; and

(e) implementing switching within the single ASIC die, such that the common elements are used regardless of which one of the different interfaces is being used, and the unique elements are used based on which one of the different interfaces is being used.

2. The method of claim 1, wherein step (e) includes providing switches within the single ASIC die that connect common elements to elements that are unique to one of the different interfaces.

3. The method of claim 2, wherein step (e) further includes selectively switching the switches based upon which one of the different interfaces is being used.

4. The method of claim 1, wherein step (e) includes monitoring a signal to determine which one of the different interfaces is being used.

5. The method of claim 1, wherein step (e) includes accessing a memory to determine which one of the different interfaces is being used.

6. The method of claim 1, wherein step (e) includes determining which one of the different interfaces is being used based on which of a plurality of terminals are electrically connected together.

7. The method of claim 1, wherein each of the different interfaces is a serial interface.

8. The method of claim 1, wherein step (a) comprises comparing at least two of the following different interfaces:

serial ATA;

Fibre Channel; and

Gigabit Ethernet.

9. A method for use with an application specific integrated circuit (ASIC) die capable of supporting at least two different interfaces, each interface for storage devices including rotatable storage medium, the ASIC die including elements that are common to the different interfaces, elements that are unique to each interface, and a plurality of switches, the method comprising:

(a) determining which one of the interfaces is being used; and

(b) controlling the switches such that the common elements are used regardless of which of the interfaces is being used, and the unique elements are used based on which of the interfaces is being used.

10. The method of claim 9, wherein step (a) comprises determining which of the interfaces is being used based on a signal received from a host.

11. The method of claim 9, wherein step (a) comprises monitoring a signal received from a host to determine which one of the interfaces is being used.

12. The method of claim 9, wherein step (a) comprises accessing a memory to determine which one of the interfaces is being used.

13. The method of claim 9, wherein step (a) comprises determining which one of the interfaces is being used based on which of a plurality of terminals are electrically connected together.

14. The method of claim 9, wherein step (a) comprises determining which one of at least two different serial interfaces is a being used, the at least two different serial interfaces comprising at least two of the following different interfaces:

serial ATA;

Fibre Channel; and

Gigabit Ethernet.

15. The method of claim 9, wherein step (a) comprises polling a signal received from a host at a first clock rate to determine which one of the interfaces is being used, the first clock rate being slower than a second clock rate used after one of the interfaces is identified.

16. The method of claim 9, further comprising a step of receiving a signal from a host using same bond pads regardless of which of the interfaces is implemented by the signal, wherein step (a) comprises determining which one of the interfaces is being used based on the signal received from the host.

17. The method of claim 16, wherein step (a) includes monitoring the signal received from the host to determine which one of the interfaces is being used.

18. The method of claim 16, wherein step (a) includes polling the signal received from the host at a first clock rate to determine which one of the interfaces is being used, the first clock rate being slower than a second clock rate used after one of the interfaces is identified.