Method for fabricating ferroelectric random access memory device
First Claim
1. A method for fabricating a ferroelectric random access memory device, comprising the steps of:
- (a) forming a first inter-layer insulation layer on a substrate providing a transistor;
(b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate;
(c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole;
(d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer;
(e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug;
(f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and
(g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.
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Accused Products
Abstract
The present invention relates to a method for fabricating a ferroelectric random access memory device. The method includes the steps of: (a) forming a first inter-layer insulation layer on a substrate providing a transistor; (b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate; (c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole; (d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer; (e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug; (f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and (g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.
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Citations
15 Claims
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1. A method for fabricating a ferroelectric random access memory device, comprising the steps of:
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(a) forming a first inter-layer insulation layer on a substrate providing a transistor;
(b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate;
(c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole;
(d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer;
(e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug;
(f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and
(g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification