Multi-functional structure for enhanced chip manufacturibility & reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor

• US 20040129938A1
• Filed: 01/08/2003
• Published: 07/08/2004
• Est. Priority Date: 01/08/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Malhotra, Sandra G., Landers, William F., Shaw, Thomas M., McGahay, Vincent J., Engel, Brett H., Davis, Charles R., Llera-Hurlburt, Diana, Goldblatt, Ronald D., Crowder, Scott W.
• Granted Patent: US 7,098,676 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.

Claims

1. Apparatus comprising:

an IC chip having an edge and an active circuit region;

a pair of barriers each comprising an electrically conductive material formed between the edge of the IC chip and the active circuit region; and

a monitor device coupled to the pair of barrier regions for monitoring electrical properties of the barrier regions, which properties indicate integrity status of the barrier regions.

2. The apparatus of claim 1, wherein the monitor device is a capacitance meter for monitoring a capacitance magnitude of the barrier regions.

3. The apparatus of claim 1, wherein the monitor device is an ohmmeter for monitoring a resistance magnitude of the barrier regions.

4. The apparatus of claim 1, wherein the barriers comprise multiple conductive horizontal layers alternating with horizontal dielectric layers vertically stacked, and wherein the alternating multiple conductive layers are electrically coupled by a via extending through each of the dielectric layers, for preventing a propagation of a crack through the IC chip.

5. The apparatus of claim 4, wherein the alternating multiple conductive layers are electrically coupled by a plurality of vias extending through each of the dielectric layers.

6. An IC chip comprising:

a top horizontal surface;

a diced edge;

an active circuit region; and

three barrier regions formed in the IC chip between the diced edge and the active circuit region, wherein;

at least one of the barrier regions comprises alternating horizontal layers of a dielectric material and a conductive material intended for preventing separations from propagating toward the active circuit region from the diced edge; and

at least one other of the barrier regions comprises alternating horizontal layers of the dielectric material and the conductive material, wherein at least one of the layers of dielectric material includes a plurality of conductive vias that electrically couple adjacent conductive layers, said at least one other of the barrier regions intended for preventing contaminants from propagating toward the active circuit region from the diced edge.

7. The IC chip of claim 6, further comprising:

a layer on the top surface of the IC chip extending from the active circuit region and terminating between a barrier region and the diced edge of the IC chip for preventing propagation of a delamination failure towards the active circuit region.

8. The IC chip of claim 7, wherein the dielectric material comprises low-k dielectric and the conductive material comprises copper.

9. Apparatus comprising:

an IC chip having a circuit region formed therein, the circuit region susceptible to manufacturing stresses that may induce structural defects in the circuit region;

a pair of electrically conductive barriers at least partially surrounding the circuit region; and

a monitor device coupled to the pair of barriers for monitoring electrical properties of the barrier regions, which properties indicate integrity status of the barrier regions.

10. The apparatus of claim 9, wherein the monitor device is a capacitance meter for monitoring a capacitance magnitude of the pair of barriers.

11. The apparatus of claim 9, wherein the monitor device is an ohmmeter for monitoring a resistance magnitude of the pair of barriers.

12. The apparatus of claim 9, wherein the barriers comprise multiple conductive horizontal layers alternating with horizontal dielectric layers vertically stacked, and wherein the alternating multiple conductive layers are electrically coupled by a via extending through each of the dielectric layers, for preventing a propagation of a crack from the circuit region.

13. The apparatus of claim 12, wherein the alternating multiple conductive layers are electrically coupled by a plurality of vias extending through each of the dielectric layers.