Thin film transistor array substrate and manufacturing method of the same
First Claim
1. A thin film transistor array substrate, comprising:
- a gate pattern including;
a gate electrode of the thin film transistor;
a gate line to which the gate electrode is connected; and
a gate pad to which the gate line is connected;
a source/drain pattern including;
a source electrode and a drain electrode of the thin film transistor;
a data line connected to the source electrode;
a data pad connected to the data line;
a storage electrode formed and superimposed with the gate line;
a semiconductor pattern formed in a low region of the substrate corresponding to the source/drain pattern;
a transparent electrode including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode formed to cover the data pad; and
a protection pattern and a gate insulation pattern stacked in the remainder region except for the region where the transparent electrode pattern is formed.
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Accused Products
Abstract
A thin film transistor array substrate has a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad connected to the gate line; a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, a data pad connected to the data line, a storage electrode formed and superimposed with the gate line; a semiconductor pattern formed in low part of the substrate; a transparent electrode pattern including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode covering the data pad; and a protection pattern and a gate insulation pattern stacked in a region other than the region where the transparent electrode pattern is formed.
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Citations
14 Claims
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1. A thin film transistor array substrate, comprising:
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a gate pattern including;
a gate electrode of the thin film transistor;
a gate line to which the gate electrode is connected; and
a gate pad to which the gate line is connected;
a source/drain pattern including;
a source electrode and a drain electrode of the thin film transistor;
a data line connected to the source electrode;
a data pad connected to the data line;
a storage electrode formed and superimposed with the gate line;
a semiconductor pattern formed in a low region of the substrate corresponding to the source/drain pattern;
a transparent electrode including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode formed to cover the data pad; and
a protection pattern and a gate insulation pattern stacked in the remainder region except for the region where the transparent electrode pattern is formed. - View Dependent Claims (2)
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3. A method of manufacturing a thin film transistor array substrate, comprising:
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forming using a first mask process, a gate electrode of the thin film transistor on the substrate, a gate line connected to the gate electrode, a gate pattern including the gate pad connected to the gate line;
forming a gate insulation film on the substrate where the gate pattern is formed;
forming using a second mask process a source electrode and a drain electrode of the thin film transistor on the gate insulation film, a data line connected to the source electrode, a data pad connected to the data line, a source/drain pattern including a storage electrode in the region superimposed with the gate line, and a semiconductor pattern formed corresponding to the source/drain pattern on the low part; and
forming using a third mask process a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode formed to cover the gate pad, a transparent electrode pattern including the data pad protection electrode formed to cover the data pad, and a gate insulation pattern and a protection film pattern stacked in the a region other than the region where the transparent electrode pattern is formed. - View Dependent Claims (4, 5, 6, 7)
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8. A thin film transistor array substrate, comprising:
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a gate electrode of the thin film transistor;
a gate line to which the gate electrode is connected; and
a gate pad to which the gate line is connected;
a source electrode and a drain electrode of the thin film transistor;
a data line connected to the source electrode;
a data pad connected to the data line;
a storage electrode formed and superimposed over the gate line;
a transparent electrode including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode formed to cover the data pad; and
a protection layer and a gate insulation layer stacked in a region of the substrate other than the region where the transparent electrode is formed. - View Dependent Claims (9)
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10. A method of manufacturing a thin film transistor array substrate, comprising:
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forming using a first mask process, a gate electrode of the thin film transistor on the substrate, a gate line connected to the gate electrode, and a gate pad connected to the gate line;
forming a gate insulation film on the substrate where the gate pad is formed;
forming using a second mask process a source electrode and a drain electrode of the thin film transistor on the gate insulation film, a data line connected to the source electrode, a data pad connected to the data line, a storage electrode superimposed over the gate line; and
forming a pixel electrode using a third mask process connected to the drain electrode and the storage electrode, a gate pad protection electrode formed to cover the gate pad, a transparent electrode, a data pad protection electrode covering the data pad, and a gate insulation pattern and a protection-film pattern stacked in the a region other than the region where the transparent electrode is formed. - View Dependent Claims (11, 12, 13, 14)
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Specification