Semiconductor chip with gate dielectrics for high-performance and low-leakage applications

• US 20040129995A1
• Filed: 01/02/2003
• Published: 07/08/2004
• Est. Priority Date: 01/02/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeo, Yee-Chia, Yang, Fu-Liang, Hu, Chenming
• Granted Patent: US 6,906,398 B2
• Time in Patent Office: Days
• US Class Current: 257/500
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

Both high performance and low leakage current devices can be formed on a single wafer without significant additional processing steps by the formation of an ultra-thin gate dielectric and a high-permittivity gate dielectric, respectively, in regions wherein switching speed and low leakage current, respectively, are desired. Logic and embedded memory regions can be performance optimized on the same integrated circuit.

Claims

1. An integrated circuit comprising:

a substrate;

a first transistor having an ultra-thin gate dielectric formed on the substrate; and

a second transistor having a gate dielectric comprised of a high-permittivity dielectric material formed on the substrate.

2. The integrated circuit of claim 1 wherein said substrate is selected from the group consisting of silicon, germanium, and silicon-on-insulator.

3. The integrated circuit of claim 1 wherein said ultra-thin gate dielectric is selected from the group consisting of silicon oxide, silicon oxynitride, and silicon nitride.

4. The integrated circuit of claim 1 wherein said high-permittivity dielectric material is selected from the group consisting of metallic oxides, oxynitrides of metals, metallic silicates, and metallic aluminates.

5. The semiconductor chip of claim 1 wherein the relative permittivity of said high-permittivity dielectric layer is greater than 8.

6. The semiconductor chip of claim 1 wherein said high-permittivity dielectric material is from 2 to 500 angstroms thick.

7. The semiconductor chip of claim 1 wherein said ultra-thin gate dielectric has an equivalent silicon oxide thickness of less than 10 Angstroms.

8. The semiconductor chip of claim 1 further comprising an interfacial layer underlying said high-permittivity dielectric material.

9. The semiconductor chip of claim 8 wherein said interfacial layer is selected from the group consisting of silicon oxide, silicon oxynitride, metallic silicates, and metallic aluminates.

10. A method of fabricating an integrated circuit comprising:

forming an isolation structure on a substrate;

forming a high-permittivity dielectric material on the substrate;

removing the high-permittivity dielectric material from a first region of the substrate while leaving the high-permittivity dielectric material over a second region of the substrate; and

forming an ultra-thin gate dielectric material over the first region.

11. The method of claim 10 further comprising:

removing a native oxide from the substrate before forming the high-permittivity dielectric material on the substrate.

12. The method of claim 10 further comprising:

forming an interfacial layer on the substrate prior to forming the high-permittivity 3 dielectric material on the substrate.

13. The method of claim 10 wherein the step of forming an ultra-thin gate dielectric comprises exposing the substrate to an ambient selected from the group consisting of H₂O, O₂, O₃, and N₂O.

14. The method of claim 10 further comprising:

forming a first gate electrode in the first region;

forming a second gate electrode in the second region;

forming first spacers adjacent the first gate electrode;

forming first source and drain regions in the substrate;

forming second spacers adjacent the second gate electrode; and

forming second source and drain regions in the substrate

15. An integrated circuit comprising:

a substrate;

a first region formed on the substrate, the first region having formed therein a plurality of first transistors, each of said plurality of first transistors including;

a first source region;

a first drain region;

a first channel region formed between the first source and first drain regions; and

a first gate electrode electrically separated from the first channel region by a high permittivity dielectric material; and

a second region formed on the substrate, the second region having formed therein a plurality of second transistors, each of the plurality of second transistors including;

a second source region;

a second drain region;

a second channel region formed between the second source and second drain regions; and

a second gate electrode electrically isolated from the second channel region by an ultra-thin dielectric material.

16. The integrated circuit of claim 15 wherein the ultra-thin dielectric material has an equivalent silicon oxide thickness of less than 10 angstroms.

17. The integrated circuit of claim 15 wherein the first region is separated from the second region by an isolation structure selected from the group consisting of shallow trench isolation, localized oxidation of silicon (LOCOS), and silicon islands formed on a silicon-on-insulator (SOI) substrate.

18. The integrated circuit of claim 15 wherein the high-permittivity dielectric material is selected from the group consisting of metallic oxides, oxynitrides of metals, metallic silicates, and metallic aluminates.

19. The integrated circuit of claim 15 wherein the high-permittivity dielectric material has a relative permittivity of at least 8.

20. The integrated circuit of claim 15 wherein the first region is a memory array.

21. The integrated circuit of claim 15 further including an interfacial layer between the substrate and the high-permittivity dielectric material.

22. The integrated circuit of claim 15 wherein the ultra-thin dielectric material is selected from the group consisting of silicon oxide, silicon oxynitride, and silicon nitride.