Single event upset hardened latch
First Claim
1. A latch circuit, comprising:
- a first latch; and
a second latch to harden the latch circuit to a single event upset, the second latch including a transmission gate having an output port to couple to only one transistor of the first latch.
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Abstract
A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.
45 Citations
19 Claims
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1. A latch circuit, comprising:
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a first latch; and
a second latch to harden the latch circuit to a single event upset, the second latch including a transmission gate having an output port to couple to only one transistor of the first latch. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A die comprising:
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a first latch having a feedback path; and
a second latch including a transmission gate including two transistors, the transmission gate located in the feedback path to render the die immune to single event upsets attacking a single node at a time. - View Dependent Claims (8, 9, 10, 11)
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12. A method, comprising:
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setting a hardened latch having a latched node to an initial value;
receiving a single event upset at the latched node;
overriding the single event upset with a second latched value to return the output value at the latched node to the initial value; and
presenting the output value at a Miller C buffer. - View Dependent Claims (13, 14, 15)
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16. A system, comprising:
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a bus;
at least one electronic unit to couple to the bus; and
a processor to couple to the bus, the processor including a plurality of hardened latches for reducing a plurality of spurious transients induced by at least one single event upset event, wherein at least one of the plurality of hardened latches includes a Miller C output buffer. - View Dependent Claims (17, 18, 19)
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Specification