Organic light emitting diode display having shield electrodes

• US 20040130516A1
• Filed: 01/23/2004
• Published: 07/08/2004
• Est. Priority Date: 02/16/2001
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Servati, Peyman, Nathan, Arokia, Karim, Karim S.
• Granted Patent: US 7,248,236 B2
• Time in Patent Office: Days
• US Class Current: 345/82
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H10K 2102/3026 Top emission
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

An organic light emitting diode (OLED) display includes at least one shield electrode between a cathode layer and an OLED drive circuit. The OLED drive circuit has at least one thin-film transistor (TFT), and the shield electrode is disposed to correspond to the thin-film transistor and closer to the cathode layer, covering an entire region between the source and drain of the thin-film transistor. The shield electrode is either grounded or tied to the gate of the thin-film transistor, to thereby minimize parasitic capacitances in the pixels of the display to enhance the display performance. The presented architecture enables high density drive circuit integration in amorphous silicon or other technologies, yet preserving a high display aperture ratio.

Claims

1. An organic light emitting diode(OLED) display, comprising:

a substrate; and

a plurality of pixels formed on the substrate and each having a means for reducing parasitic capacitances causing leakage currents therein during operations thereof.

2. The OLED display as claimed in claim 1, wherein the parasitic capacitances-reducing means is grounded.

3. The OLED display as claimed in claim 1, wherein the parasitic capacitance reducing means is formed with at least one shield electrode of electric conductor.

4. The OLED display as claimed in claim 3, wherein the pixels each include:

an OLED for emitting light; and

a drive circuit for electrically driving the OLED, the at least one shield electrode being disposed between the OLED layer and the drive circuit.

5. The OLED display as claimed in claim 4, wherein the OLED includes an anode layer, an electroluminescent layer, and a cathode layer, and the drive circuit has at least one thin-film transistor, the at least one shield electrode being disposed to correspond to the at least one thin-film transistor between the cathode layer and the at least one thin-film transistor.

6. The OLED display as claimed in claim 5, wherein the parasitic capacitances-reducing means is electrically tied to a gate of the at least one TFT transistor.

7. The OLED display as claimed in claim 5, wherein the at least one shield electrode covers an entire region between a source and a drain of the at least one thin-film transistor.

8. The OLED display as claimed in claim 7, wherein the at least one shield electrode is disposed closer to the cathode layer.

9. The OLED display as claimed in claim 8, wherein the OLED and the drive circuit are vertically stacked over the substrate.

10. The OLED display as claimed in claim 9, wherein the pixels are each formed for a top emission.

11. The OLED display as claimed in claim 10, wherein the drive circuit is formed in inverted staggered thin-film structures.

12. The OLED display as claimed in claim 11, wherein the at least one shield electrode is formed of a standard metallization layer in LCD process or any other metallization.

13. The OLED display as claimed in claim 11, wherein the at least one shield electrode is formed in a rectangular shape.