Shared T1/E1 signaling bit processor
First Claim
1. A communication apparatus for interfacing robbed signaling bits with respect to serial digital communication signals transported over a serial communication path comprising:
- a signaling bit capture memory that is configured to receive and store signaling bits extracted from serial digital communication signals having different signaling protocols; and
a receiver subsystem processor configured to be coupled with said serial communication path and said signaling bit capture memory and being operative to controllably extract robbed bit signals from serial digital communication signals having any of said different signaling protocols and stored extracted robbed bit signals in said signaling bit capture memory.
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Abstract
A shared T1/E1 signaling bit processor interfaces with either T1 or E1 traffic, and controllably performs robbed bit signal extraction and insertion for T1/E1 signaling protocol using a common set of input/output circuitry and associated decode/control logic therefor. A receiver subsystem controllably samples and extracts signaling bits from selected time slots within serial frames of data incoming from the network to the DTE for delivery to the control processor; a transmitter subsystem controllably inserts signaling bits into selected signaling channels of serial frames of data outgoing from the DTE to the network.
55 Citations
17 Claims
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1. A communication apparatus for interfacing robbed signaling bits with respect to serial digital communication signals transported over a serial communication path comprising:
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a signaling bit capture memory that is configured to receive and store signaling bits extracted from serial digital communication signals having different signaling protocols; and
a receiver subsystem processor configured to be coupled with said serial communication path and said signaling bit capture memory and being operative to controllably extract robbed bit signals from serial digital communication signals having any of said different signaling protocols and stored extracted robbed bit signals in said signaling bit capture memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A communication apparatus for interfacing robbed signaling bits with respect to serial digital communication signals transported over a serial communication path comprising:
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a signaling bit memory that is configured to receive and store signaling bits for insertion into serial digital communication signals having any of a plurality of different signaling protocols; and
a transmitter configured to be coupled with said serial communication path and said signaling bit memory and being operative to controllably perform robbed bit signal insertion from said memory into serial digital communication signals having any of said plurality of different signaling protocols. - View Dependent Claims (10, 11)
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12. A method for interfacing robbed signaling bits with respect to serial digital communication signals transported over a serial communication path comprising the steps of:
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(a) providing a signaling bit capture memory that is configured to receive and store signaling bits extracted from serial digital communication signals having different signaling protocols; and
(b) performing robbed bit signal extraction from serial digital communication signals transported over said serial communication path having any of said differing signaling protocols and storing said signaling bits in aid signaling bit capture memory;
(c) providing a signaling bit read out memory which is configured to store signaling bits for insertion into serial digital communication signals having any of said different signaling protocols; and
(d) controllably inserting signaling bits stored in said signaling bit read out memory in step (c) into serial digital communication signals having any of said different signaling protocols. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification