Double-sampled, sample-and-hold circuit with downconversion

• US 20040131131A1
• Filed: 01/03/2003
• Published: 07/08/2004
• Est. Priority Date: 01/03/2003
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Peach, Charles T., Soumyanath, Krishnamurthy
• Application Number:
  US10/336,618
• Publication Number:
  US 20040131131A1
• Time in Patent Office: Days
• US Class Current: 375/316
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

A device (200, FIG. 2) includes receive hardware (204) which performs analog-to-digital conversion. In accordance with an embodiment of the invention, the receive hardware includes a pipelined analog-to-digital converter (320, FIG. 3). Sample-and-hold circuitry (410, FIG. 4) associated with the analog-to-digital converter is configured (FIGS. 8, and 12-14) and switched (FIG. 7) in a manner that provides intermediate frequency to baseband downconversion and skew-insensitive double-sampling.

Claims

1. A circuit comprising:

a sampling circuit configured to double-sample a first input signal and a second input signal, and to provide a first output voltage and a second output voltage to an amplifier, wherein the sampling circuit is switchable in a manner that downconverts the first input signal and the second input signal; and

the amplifier, coupled to the first sampling circuit, configured to hold the first output voltage and the second output voltage.

2. The circuit of claim 1, wherein the sampling circuit includes one or more envelope switches configured to provide a single sampling instant.

3. The circuit of claim 1, wherein the sampling circuit includes

a first half circuit coupled to the amplifier, which includes a first capacitor that is charged by the first input signal when a first set of sampling switches are closed, and a second capacitor that is charged by the second input signal when a second set of sampling switches are closed;

and

a second half circuit coupled to the amplifier, which includes a third capacitor that is charged by the second input signal when a third set of sampling switches are closed, which are synchronized with the second set of sampling switches, and a fourth capacitor that is charged by the first input signal when a fourth set of sampling switches are closed, which are synchronized with the first set of sampling switches.

4. The circuit of claim 3, wherein the second half circuit is coupled to the amplifier in a manner that the second output voltage provided by the second half circuit is inverted.

5. The circuit of claim 1, wherein the sampling circuit includes

a first capacitor;

a second capacitor;

a first set of switches that are switchable together, and that are coupled to the first capacitor and the second capacitor, so that when the first set of switches is closed, the first capacitor is charged by the first input signal, and the second capacitor is charged by the second input signal;

a third capacitor;

a fourth capacitor; and

a second set of switches that are switchable together, and that are coupled to the third capacitor and the fourth capacitor, so that when the second set of switches is closed, the third capacitor is charged by the first input signal, and the fourth capacitor is charged by the second input signal, and

wherein when the first set of switches are closed, a first output voltage across the third capacitor and a second output voltage across the fourth capacitor are held by the amplifier, and when the second set of switches are closed, a third output voltage across the first capacitor and a fourth output voltage across the second capacitor are held by the amplifier.

6. The circuit of claim 1, wherein the sampling circuit is configured to downconvert the first input signal and the second input signal from an intermediate frequency to baseband.

7. The circuit of claim 1, wherein the sampling circuit is configured to separate the I and Q components of first input signal and the second input signal.

8. The circuit of claim 1, further comprising a pipelined converter, coupled to the amplifier.

9. The circuit of claim 1, wherein the circuit is a complementary metal-oxide semiconductor (CMOS) integrated circuit.

10. An apparatus comprising:

an amplifier, which receives an input signal and produces an amplified signal;

a mixer, which receives and downconverts the amplified signal to an intermediate frequency (IF) input signal;

a variable gain amplifier, which adjusts a power level of the IF input signal based on a dynamic range of an analog-to-digital converter; and

the analog-to-digital converter, which receives an amplified IF signal from the variable gain amplifier, downconverts the amplified IF signal, and converts the amplified IF signal into digital information, wherein the analog-to-digital converter includes

a sampling circuit configured to double-sample a first input signal and a second input signal, and to provide a first output voltage and a second output voltage to a second amplifier, wherein the sampling circuit is switchable in a manner that downconverts the first input signal and the second input signal,

the second amplifier, coupled to the first sampling circuit, configured to hold the first output voltage and the second output voltage, and

a converter, coupled to the second amplifier.

11. The apparatus of claim 10, wherein the sampling circuit includes one or more envelope switches configured to provide a single sampling instant.

12. The apparatus of claim 10, wherein the sampling circuit includes

a first capacitor;

a second capacitor;

a first set of switches that are switchable together, and that are coupled to the first capacitor and the second capacitor, so that when the first set of switches is closed, the first capacitor is charged by the first input signal, and the second capacitor is charged by the second input signal;

a third capacitor;

a fourth capacitor; and

a second set of switches that are switchable together, and that are coupled to the third capacitor and the fourth capacitor, so that when the second set of switches is closed, the third capacitor is charged by the first input signal, and the fourth capacitor is charged by the second input signal, and

wherein when the first set of switches are closed, a first output voltage across the third capacitor and a second output voltage across the fourth capacitor are held by the amplifier, and when the second set of switches are closed, a third output voltage across the first capacitor and a fourth output voltage across the second capacitor are held by the amplifier.

13. The apparatus of claim 10, wherein the sampling circuit is configured to downconvert the first input signal and the second input signal from an IF to baseband.

14. The apparatus of claim 10, wherein the sampling circuit is configured to separate the I and Q components of first input signal and the second input signal.

15. The apparatus of claim 10, wherein the converter is a pipelined converter.

16. A device comprising:

receive hardware, which includes

a sampling circuit configured to double-sample a first input signal and a second input signal, and to provide a first output voltage and a second output voltage to an amplifier, wherein the sampling circuit is switchable in a manner that downconverts the first input signal and the second input signal,

the amplifier, coupled to the first sampling circuit, configured to hold the first output voltage and the second output voltage, and

a converter, coupled to the amplifier, which produces digital information; and

one or more processors, coupled to the receive hardware, capable of processing the digital information.

17. The device of claim 16, further comprising an antenna, coupled to the receive hardware, which receives an analog radio frequency signal.

18. The device of claim 16, wherein the sampling circuit includes one or more envelope switches configured to provide a single sampling instant.

19. The device of claim 16, wherein the sampling circuit is configured to separate the I and Q components of first input signal and the second input signal.

20. The device of claim 16, wherein the converter is a pipelined converter.

21. A method for downconverting an analog signal and performing analog-to-digital conversion, comprising:

providing a sampling circuit that receives a differential input signal including a first input signal and a second input signal, wherein the sampling circuit includes

a first capacitor,

a second capacitor,

a first set of switches that are switchable together, and that are coupled to the first capacitor and the second capacitor,

a third capacitor,

a fourth capacitor, and

a second set of switches that are switchable together, and that are coupled to the third capacitor and the fourth capacitor;

closing the first set of switches, which causes the first capacitor to be charged by the first input signal, the second capacitor to be charged by the second input signal, and a first output voltage across the third capacitor and a second output voltage across the fourth capacitor to be provided to an amplifier;

opening the first set of switches;

closing the second set of switches, which causes the third capacitor to be charged by the first input signal, the fourth capacitor to be charged by the second input signal, and a third output voltage across the first capacitor and a fourth output voltage across the second capacitor to be provided to the amplifier; and

opening the second set of switches.

22. The method of claim 21, further comprising closing and opening one or more envelope switches of the sampling circuit, in order to provide a single sampling instant.

23. The method of claim 21, further comprising separating I and Q components of first input signal and the second input signal.

24. The method of claim 21, further comprising converting analog outputs of the amplifier into digital information using a pipelined converter.

25. A method for downconverting an analog signal and performing analog-to-digital conversion, comprising:

double-sampling a first input signal and a second input signal, using a sampling circuit, to provide a first output voltage and a second output voltage;

downconverting the first input signal and the second input signal using the sampling circuit; and

holding the first output voltage and the second output voltage.

26. The method of claim 25, wherein downconverting the first input signal and the second input signal downconverts the first input signal and the second input signal from an intermediate frequency to baseband.

27. The method of claim 25, further comprising separating the I and Q components of first input signal and the second input signal.