Ultra-high capacitance device based on nanostructures

• US 20040131774A1
• Filed: 12/17/2003
• Published: 07/08/2004
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Sarah E. Kim, Scot A. Kellar
• Original Assignee: Sarah E. Kim, Scot A. Kellar
• Inventors: Kim, Sarah E., Kellar, Scot A.
• Granted Patent: US 7,271,434 B2
• Time in Patent Office: Days
• US Class Current: 427/248.1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/81 Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: Y10S 977/70 Nanostructure
• CPC Class Codes: Y10S 977/72 On an electrically conducting, semi-conducting, or semi-insulating substrate
• CPC Class Codes: Y10S 977/721 On a silicon substrate
• CPC Class Codes: Y10S 977/723 On an electrically insulating substrate
• CPC Class Codes: Y10S 977/902 Specified use of nanostructure
• CPC Class Codes: Y10S 977/963 Miscellaneous
• CPC Class Codes: Y10T 428/24802 Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]

Abstract

The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric.

The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Claims

1. A method comprising:

providing a substrate;

forming a lower conductor over said substrate;

forming a conducting nanostructure over said lower conductor;

forming a thin dielectric over said conducting nanostructure; and

forming an upper conductor over said thin dielectric.

2. The method of claim 1 wherein said conducting nanostructure is formed by self-assembly.

3. The method of claim 1 wherein said thin dielectric is formed by Atomic Layer Deposition (ALD).

4. The method of claim 1 wherein said conducting nanostructure is formed by Chemical Vapor Deposition (CVD).

5. The method of claim 1 wherein said conducting nanostructure is formed selectively.

6. The method of claim 1 wherein said conducting nanostructure is formed non-selectively.

7. A device comprising:

a substrate;

a lower conductor disposed over said substrate;

a conducting nanostructure disposed over said lower conductor;

a thin dielectric disposed over said conducting nanostructure; and

an upper conductor disposed over said thin dielectric.

8. The device of claim 7 wherein said thin dielectric comprises an insulating nanostructure.

9. The device of claim 8 wherein said conducting nanostructure and said insulating nanostructure are attached in a nanochain.

10. The device of claim 7 wherein said thin dielectric comprises a high k value material.

11. The device of claim 7 wherein said conducting nanostructure comprises a Carbon nanotube.

12. The device of claim 7 wherein said upper conductor comprises a material that is either difficult to oxidize or else forms a conductive oxide.

13. A method comprising:

providing a substrate;

forming an insulating nanostructure over said substrate;

forming a thin conductor over said insulating nanostructure;

forming a thin dielectric over said thin conductor; and

forming an upper conductor over said thin dielectric.

14. The method of claim 13 wherein said insulating nanostructure is formed by self-assembly.

15. The method of claim 13 wherein said thin dielectric is formed by Atomic Layer Deposition (ALD).

16. The method of claim 13 wherein said insulating nanostructure is formed by Chemical Vapor Deposition (CVD).

17. The method of claim 13 wherein said insulating nanostructure is formed selectively.

18. A device comprising:

a substrate;

an insulating nanostructure disposed over said substrate;

a thin conductor disposed over said insulating nanostructure;

a thin dielectric disposed over said thin conductor; and

an upper conductor disposed over said thin dielectric.

19. The device of claim 18 wherein said thin dielectric comprises an insulating nanostructure.

20. The device of claim 18 wherein said thin dielectric comprises a high k value material.

21. The device of claim 18 wherein said upper conductor comprises a material that is either difficult to oxidize or else forms a conductive oxide.