Delay distribution calculation method, circuit evaluation method and false path extraction method

• US 20040132224A1
• Filed: 12/19/2003
• Published: 07/08/2004
• Est. Priority Date: 11/22/2000
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Fukui, Masahiro, Tanaka, Masakazu, Tsukiyama, Shuji
• Granted Patent: US 7,131,082 B2
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: G05B 19/0421 Multiprocessor system
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]

Abstract

Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Claims

1. A method for calculating delay distribution in an integrated circuit to be designed, wherein the delay distribution is calculated based on correlation information indicating a correlation of performance between interconnects or elements that are included in the integrated circuit.

2. The method according to claim 1, wherein the correlation information indicates a correlation of delay as the correlation of performance.

3. The method according to claim 1, wherein the correlation information is represented by a correlation coefficient in performance distribution.

4. The method according to claim 1, comprising the steps of:

generating a graph representing the integrated circuit based on circuit information indicating connection between elements in the integrated circuit; and

calculating delay distribution of each vertex in the graph by using performance distribution information and the correlation information, the performance distribution information indicating performance distribution of the interconnects and the elements that are included in the integrated circuit.

5. The method according to claim 4, wherein

the calculation step includes

a first step of selecting from the graph a vertex that does not belong to a set of vertices whose delay distribution has been calculated as a vertex for calculation, and

a second step of calculating for the vertex selected in the first step the delay distribution and a correlation of performance with each vertex belonging to the set, based on the performance distribution information and the correlation information, and

the first and second steps are repeatedly conducted while adding to the set the vertex whose delay distribution has been calculated.

6. The method according to claim 1, comprising the step of producing the correlation information based on layout of the integrated circuit by using correlation characteristics information, the correlation characteristics information indicating a relation between the correlation of performance between the interconnects or the elements and layout characteristics.

7. The method according to claim 6, wherein the correlation characteristics information indicates at least a relation between a distance between the elements and the correlation of performance.

8. The method according to claim 6, wherein the correlation characteristics information indicates at least a relation between orientation of the elements and the correlation of performance.

9. The method according to claim 6, wherein the correlation characteristics information indicates at least a relation between presence/absence or length of a common part of two interconnects and the correlation of performance.

10. The method according to claim 6, comprising the step of evaluating characteristics of each interconnect or element in an integrated circuit for characteristics evaluation, and producing the correlation characteristics information based on the evaluation result and layout of the integrated circuit for characteristics evaluation.

11. A method for evaluating an integrated circuit to be designed, comprising:

a first step of producing an equivalent circuit that does not include a signal transmission path corresponding to a false path, based on circuit information indicating connection between components in the integrated circuit; and

a second step of evaluating the integrated circuit by using the equivalent circuit produced in the first step.

12. The method according to claim 11, wherein false path information indicating the false path is used, and the false path information represents the false path by two vertices on a graph representing the integrated circuit.

13. The method according to claim 12, wherein the first step includes the steps of

extracting a first partial circuit provided with a first vertex as an input and a second vertex as an output, the first vertex and the second vertex are two vertices representing the false path,

making a copy of the first partial circuit as a second partial circuit, and

modifying connection of the first and second partial circuits and another circuit such that there exists no path from the first vertex toward the second vertex.

14. The method according to claim 13, wherein in the modification step, provided that “

In”

is a set of initial vertices of each edge coming into the first partial circuit other than the first vertex and “

Out”

is a set of terminal vertices of each edge going out from the first partial circuit other than the second vertex, the connection is modified such that one of the first and second partial circuits is connected to the first vertex, “

In” and

“

Out” and

is not connected to the second vertex as well as the other partial circuit is connected to the second vertex and “

In” and

is not connected to the first vertex and “

Out”

.

15. The method according to claim 13, wherein in the modification step, provided that “

In”

is a set of initial vertices of each edge coming into the first partial circuit other than the first vertex and “

Out”

is a set of terminal vertices of each edge going out from the first partial circuit other than the second vertex, the connection is modified such that one of the first and second partial circuits is connected to the first vertex and “

Out” and

is not connected to the second vertex and “

In”

as well as the other partial circuit is connected to the second vertex, “

In” and

“

Out” and

is not connected to the first vertex.

16. A method for extracting a false path in an integrated circuit to be designed, wherein the false path is extracted using an activating condition of a non-control signal edge within each logic gate included in the integrated circuit.

17. The method according to claim 16, comprising the steps of:

propagating a logic value listed in the activating condition of a non-control signal edge within a first gate by a propagation process;

conducting repeatedly the propagation step while the value to be propagated is a control signal; and

detecting a path from the first gate to a second gate as the false path when the propagated value is inconsistent with the activating condition of a non-control signal edge within the second gate.