Lithography device for semiconductor circuit pattern generator
First Claim
1. A method of forming a random-access memory, comprising the steps of:
- fabricating a memory circuit on a first substrate;
fabricating a memory controller circuit on a second substrate; and
bonding the first and second substrates to form interconnects between the memory circuit and the memory controller circuit, neither the first substrate alone nor the second substrate alone being sufficient to provide random access data storage.
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Accused Products
Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
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Citations
87 Claims
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1. A method of forming a random-access memory, comprising the steps of:
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fabricating a memory circuit on a first substrate;
fabricating a memory controller circuit on a second substrate; and
bonding the first and second substrates to form interconnects between the memory circuit and the memory controller circuit, neither the first substrate alone nor the second substrate alone being sufficient to provide random access data storage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method of information processing using a stacked integrated circuit memory including a memory controller layer and multiple memory layers, the method comprising the steps of:
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initiating a memory access; and
independently routing data vertically between the memory controller layer and selected storage locations within each of a plurality of equal size memory blocks. - View Dependent Claims (32, 33, 34, 35, 36, 37)
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38. A stacked integrated circuit memory comprising:
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a first substantially rigid substrate having formed thereon one of a memory circuit and a memory controller circuit; and
at least one substantially flexible substrate having formed thereon the other of said memory circuit and said memory controller circuit and being bonded to the first substrate. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
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62. A method of bonding together multiple substrates each having integrated circuits formed thereon to form interconnections between the integrated circuits, the method comprising the steps of:
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processing a mating surface on each of first and second substrates to achieve substantial planarity of the mating surfaces;
forming mating, fine-grain interconnect patterns on the mating surfaces; and
performing fine-grain, planar thermal diffusion bonding of the mating surfaces. - View Dependent Claims (63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87)
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Specification