Polymer film metalization

• US 20040132285A1
• Filed: 01/06/2003
• Published: 07/08/2004
• Est. Priority Date: 01/06/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Andideh, Ebrahim, Diana, Daniel C.
• Granted Patent: US 6,890,813 B2
• Time in Patent Office: Days
• US Class Current: 438/678
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties

Abstract

Embodiments in accordance with the present invention eliminate the need for a subtractive metal patterning process to pattern the electrode above a ferroelectric polymer. Instead, a selective electroless deposition process is used. A conductive polymer is used as a seed layer for the electroless plating of the metal electrode. A cost saving is provided by eliminating the chemical costs associated with conventional resist removal processing. The methods also potentially eliminate the requirement for aggressive and environmentally unsafe chemical-based photoresist removal processes.

Claims

1. A method for forming a conductive layer on a ferroelectric polymer layer, comprising:

forming a conductive polymer layer on the ferroelectric polymer layer;

using conventional lithography and etch processes to pattern the conductive polymer;

removing the patterning photoresist using etch and clean processes; and

depositing a conductive layer on the conductive polymer layer using an electroless plating process.

2. The method of claim 1, wherein forming a conductive polymer layer on the ferroelectric polymer layer comprises:

forming a conductive polymer layer on the ferroelectric polymer layer using a spin deposition and cure process.

3. The method of claim 1, wherein using conventional lithography and etch processes to pattern the conductive polymer comprises:

using photoresist spin deposition to form the layer of photoresist on the conductive polymer layer, and

exposing predetermined areas of the photoresist to a curing process.

4. The method of claim 1, wherein using conventional lithography and etch processes to pattern the conductive polymer comprises:

using conventional lithography and plasma etch processes to pattern the conductive polymer.

5. The method of claim 1, wherein depositing a conductive layer on the conductive polymer layer using an electroless plating process comprises:

depositing a conductive layer on the conductive polymer layer using an electroless plating process, optimizing the deposition process to minimize conductive layer deposition on the sidewalls of the conductive polymer.

6. A method for making a semiconductor substrate comprising:

providing a substrate including a silicon layer, a silicon dioxide layer, a conductive layer and a ferroelectric polymer layer;

forming a conductive polymer layer on the ferroelectric polymer layer;

using conventional lithography and etch processes to pattern the conductive polymer;

removing the patterning photoresist using etch and clean processes; and

depositing a conductive layer on the conductive polymer layer using an electroless plating process.

7. The method of claim 6, wherein forming a conductive polymer layer on the ferroelectric polymer layer comprises:

forming a conductive polymer layer on the ferroelectric polymer layer using a spin deposition and cure process.

8. The method of claim 6, wherein using conventional lithography and etch processes to pattern the conductive polymer comprises:

using photoresist spin deposition to form the layer of photoresist on the conductive polymer layer, and

exposing predetermined areas of the photoresist to a curing process.

9. The method of claim 6, wherein using conventional lithography and etch processes to pattern the conductive polymer comprises:

using conventional lithography and plasma etch processes to pattern the conductive polymer.

10. The method of claim 6, wherein depositing a conductive layer on the conductive polymer layer using an electroless plating process comprises:

depositing a conductive layer on the conductive polymer layer using an electroless plating process, optimizing the deposition process to minimize conductive layer deposition on the sidewalls of the conductive polymer.

11. A semiconductor substrate comprising:

a substrate including a silicon layer, a silicon dioxide layer, a first conductive layer, and a ferroelectric polymer layer;

a patterned conductive polymer layer covering the ferroelectric polymer layer; and

a conductive layer on the patterned conductive polymer layer, the conductive layer comprising electroless metal.

12. The semiconductor substrate of claim 11, wherein the conductive layer and the conductive polymer have not been exposed to a metal etch process.