Adaptable datapath for a digital processing system

• US 20040133745A1
• Filed: 07/23/2003
• Published: 07/08/2004
• Est. Priority Date: 10/28/2002
• Status: Abandoned Application

• Current Assignee: QST Holdings LLC
• Original Assignee: QuickSilver Controls, Inc.
• Inventors: Ramchandran, Amit
• Application Number:
  US10/626,833
• Publication Number:
  US 20040133745A1
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., discrete cosine transform (DCT), fast-Fourier transform (FFT) and other operations. Other features are provided.

Claims

1. A data path circuit in a digital processing device, wherein the data path circuit is coupled to a memory bus for obtaining values from a memory, the data path circuit comprising

a first plurality of data lines;

a first data address generator for coupling the first plurality of data lines to the memory bus so that a value from the memory transferred by the memory bus can be placed onto the first plurality of data lines;

one or more functional units for performing a digital operation coupled to the plurality of data lines; and

a register coupled to the first plurality of data lines, wherein the register selectively stores a value from the first plurality of data lines so that the value is selectively available on the first plurality of data lines.

2. The data path circuit of claim 1, wherein the register includes a register file for selectively storing multiple values from the first plurality of data lines and for selectively applying the stored multiple values to the first plurality of data lines.

3. The data path circuit of claim 1, further comprising

a control signal coupled to the register for controlling storage of a value from the first plurality of data lines.

4. The data path circuit of claim 1, wherein a data field is used to select loading of a value on the memory bus of selectable bit width.

5. The data path circuit of claim 1, further comprising

a second plurality of data lines;

a second data address generator for coupling the second plurality of data lines to the memory bus so that a value from the memory transferred by the memory bus can be placed onto the second plurality of data lines; and

wherein the second data address generator is responsive to a control signal for selectively providing a data value from the first plurality of data lines to the second plurality of data lines.

8. The data path circuit of claim 1, wherein the functional units include a multiplier and accumulator, the data path circuit further comprising

a coupling of the multiplier to the plurality of data path lines;

a coupling of the accumulator to the plurality of data path lines;

direct data lines coupled between the multiplier and the accumulator.

9. The data path circuit of claim 8, wherein the direct data lines are uni-directional for transferring data from the multiplier to the accumulator.

6. A data path circuit in a digital processing device, wherein the data path circuit is coupled to a memory bus for obtaining values from a memory, the data path circuit comprising

a plurality of groups of data lines;

a plurality of data address generators for coupling the plurality of groups of data lines to the memory bus so that a value from the memory transferred by the memory bus can be placed onto a group of data lines;

one or more functional units for performing a digital operation coupled to the plurality of groups of data lines; and

a plurality of registers coupled to each group of data lines on a one-to-one correspondence, wherein the plurality of registers selectively store values from the plurality of groups of data lines so that the values are selectively available on the plurality of groups of data lines.

7. The data path circuit of claim 6, wherein 8 groups of 16 data lines are used, wherein each group of data lines is coupled to a register file capable of storing 8 16-bit words, wherein-each of the data address generators can selectively provide a value on a first group of data lines to a second group of data lines.

10. A digital processing system comprising

a multiplier;

an accumulator;

a configurable data path coupled to the multiplier and the accumulator; and

a direct data path coupled between the multiplier and the accumulator.